Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8417795 |
1 |
|
|
T22 |
338 |
|
T1 |
14601 |
|
T11 |
23300 |
| auto[1] |
6291700 |
1 |
|
|
T1 |
11764 |
|
T11 |
18294 |
|
T13 |
133 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13902531 |
1 |
|
|
T22 |
338 |
|
T1 |
25029 |
|
T11 |
39386 |
| auto[1] |
806964 |
1 |
|
|
T1 |
1336 |
|
T11 |
2208 |
|
T13 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8418768 |
1 |
|
|
T22 |
338 |
|
T1 |
14081 |
|
T11 |
23969 |
| auto[1] |
6290727 |
1 |
|
|
T1 |
12284 |
|
T11 |
17625 |
|
T13 |
154 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2753347 |
1 |
|
|
T1 |
5680 |
|
T11 |
8225 |
|
T13 |
70 |
| auto[1] |
auto[0] |
auto[1] |
404724 |
1 |
|
|
T1 |
649 |
|
T11 |
1260 |
|
T13 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2730416 |
1 |
|
|
T1 |
5268 |
|
T11 |
7192 |
|
T13 |
70 |
| auto[1] |
auto[1] |
auto[1] |
402240 |
1 |
|
|
T1 |
687 |
|
T11 |
948 |
|
T13 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |