Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8406028 |
1 |
|
|
T22 |
338 |
|
T1 |
14110 |
|
T11 |
21815 |
auto[1] |
6303467 |
1 |
|
|
T1 |
12255 |
|
T11 |
19779 |
|
T13 |
111 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12141449 |
1 |
|
|
T22 |
338 |
|
T1 |
18601 |
|
T11 |
29775 |
auto[1] |
2568046 |
1 |
|
|
T1 |
7764 |
|
T11 |
11819 |
|
T13 |
77 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8424012 |
1 |
|
|
T22 |
338 |
|
T1 |
14207 |
|
T11 |
22135 |
auto[1] |
6285483 |
1 |
|
|
T1 |
12158 |
|
T11 |
19459 |
|
T13 |
173 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1854351 |
1 |
|
|
T1 |
2196 |
|
T11 |
3762 |
|
T13 |
52 |
auto[1] |
auto[0] |
auto[1] |
1279625 |
1 |
|
|
T1 |
3945 |
|
T11 |
5881 |
|
T13 |
51 |
auto[1] |
auto[1] |
auto[0] |
1863086 |
1 |
|
|
T1 |
2198 |
|
T11 |
3878 |
|
T13 |
44 |
auto[1] |
auto[1] |
auto[1] |
1288421 |
1 |
|
|
T1 |
3819 |
|
T11 |
5938 |
|
T13 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |