Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8388299 |
1 |
|
|
T22 |
338 |
|
T1 |
14945 |
|
T11 |
21977 |
auto[1] |
6321196 |
1 |
|
|
T1 |
11420 |
|
T11 |
19617 |
|
T13 |
182 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12138215 |
1 |
|
|
T22 |
338 |
|
T1 |
18523 |
|
T11 |
29410 |
auto[1] |
2571280 |
1 |
|
|
T1 |
7842 |
|
T11 |
12184 |
|
T13 |
88 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8403920 |
1 |
|
|
T22 |
338 |
|
T1 |
13846 |
|
T11 |
21647 |
auto[1] |
6305575 |
1 |
|
|
T1 |
12519 |
|
T11 |
19947 |
|
T13 |
143 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1857652 |
1 |
|
|
T1 |
2352 |
|
T11 |
3886 |
|
T13 |
10 |
auto[1] |
auto[0] |
auto[1] |
1278595 |
1 |
|
|
T1 |
4092 |
|
T11 |
6012 |
|
T13 |
17 |
auto[1] |
auto[1] |
auto[0] |
1876643 |
1 |
|
|
T1 |
2325 |
|
T11 |
3877 |
|
T13 |
45 |
auto[1] |
auto[1] |
auto[1] |
1292685 |
1 |
|
|
T1 |
3750 |
|
T11 |
6172 |
|
T13 |
71 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |