Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8422135 |
1 |
|
|
T22 |
338 |
|
T1 |
15410 |
|
T11 |
22380 |
auto[1] |
6287360 |
1 |
|
|
T1 |
10955 |
|
T11 |
19214 |
|
T13 |
159 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12134822 |
1 |
|
|
T22 |
338 |
|
T1 |
18715 |
|
T11 |
30488 |
auto[1] |
2574673 |
1 |
|
|
T1 |
7650 |
|
T11 |
11106 |
|
T13 |
32 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8396317 |
1 |
|
|
T22 |
338 |
|
T1 |
14399 |
|
T11 |
23502 |
auto[1] |
6313178 |
1 |
|
|
T1 |
11966 |
|
T11 |
18092 |
|
T13 |
73 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1866504 |
1 |
|
|
T1 |
2385 |
|
T11 |
3378 |
|
T13 |
11 |
auto[1] |
auto[0] |
auto[1] |
1288250 |
1 |
|
|
T1 |
4118 |
|
T11 |
5279 |
|
T13 |
8 |
auto[1] |
auto[1] |
auto[0] |
1872001 |
1 |
|
|
T1 |
1931 |
|
T11 |
3608 |
|
T13 |
30 |
auto[1] |
auto[1] |
auto[1] |
1286423 |
1 |
|
|
T1 |
3532 |
|
T11 |
5827 |
|
T13 |
24 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |