Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8396964 |
1 |
|
|
T22 |
338 |
|
T1 |
14671 |
|
T11 |
24612 |
auto[1] |
6312531 |
1 |
|
|
T1 |
11694 |
|
T11 |
16982 |
|
T13 |
166 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12136150 |
1 |
|
|
T22 |
338 |
|
T1 |
18493 |
|
T11 |
30273 |
auto[1] |
2573345 |
1 |
|
|
T1 |
7872 |
|
T11 |
11321 |
|
T13 |
95 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8406258 |
1 |
|
|
T22 |
338 |
|
T1 |
14267 |
|
T11 |
23031 |
auto[1] |
6303237 |
1 |
|
|
T1 |
12098 |
|
T11 |
18563 |
|
T13 |
166 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1861565 |
1 |
|
|
T1 |
2060 |
|
T11 |
3944 |
|
T13 |
22 |
auto[1] |
auto[0] |
auto[1] |
1286761 |
1 |
|
|
T1 |
3813 |
|
T11 |
6089 |
|
T13 |
34 |
auto[1] |
auto[1] |
auto[0] |
1868327 |
1 |
|
|
T1 |
2166 |
|
T11 |
3298 |
|
T13 |
49 |
auto[1] |
auto[1] |
auto[1] |
1286584 |
1 |
|
|
T1 |
4059 |
|
T11 |
5232 |
|
T13 |
61 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |