Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8392401 |
1 |
|
|
T22 |
338 |
|
T1 |
15086 |
|
T11 |
22554 |
auto[1] |
6317094 |
1 |
|
|
T1 |
11279 |
|
T11 |
19040 |
|
T13 |
141 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12135153 |
1 |
|
|
T22 |
338 |
|
T1 |
18414 |
|
T11 |
30562 |
auto[1] |
2574342 |
1 |
|
|
T1 |
7951 |
|
T11 |
11032 |
|
T13 |
86 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8396450 |
1 |
|
|
T22 |
338 |
|
T1 |
14260 |
|
T11 |
23524 |
auto[1] |
6313045 |
1 |
|
|
T1 |
12105 |
|
T11 |
18070 |
|
T13 |
142 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1855905 |
1 |
|
|
T1 |
2166 |
|
T11 |
3501 |
|
T13 |
31 |
auto[1] |
auto[0] |
auto[1] |
1278547 |
1 |
|
|
T1 |
4142 |
|
T11 |
5621 |
|
T13 |
26 |
auto[1] |
auto[1] |
auto[0] |
1882798 |
1 |
|
|
T1 |
1988 |
|
T11 |
3537 |
|
T13 |
25 |
auto[1] |
auto[1] |
auto[1] |
1295795 |
1 |
|
|
T1 |
3809 |
|
T11 |
5411 |
|
T13 |
60 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |