Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8386347 |
1 |
|
|
T22 |
338 |
|
T1 |
14926 |
|
T11 |
21742 |
auto[1] |
6323148 |
1 |
|
|
T1 |
11439 |
|
T11 |
19852 |
|
T13 |
105 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12143341 |
1 |
|
|
T22 |
338 |
|
T1 |
18306 |
|
T11 |
30294 |
auto[1] |
2566154 |
1 |
|
|
T1 |
8059 |
|
T11 |
11300 |
|
T13 |
72 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8415425 |
1 |
|
|
T22 |
338 |
|
T1 |
13909 |
|
T11 |
23561 |
auto[1] |
6294070 |
1 |
|
|
T1 |
12456 |
|
T11 |
18033 |
|
T13 |
124 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1857130 |
1 |
|
|
T1 |
2170 |
|
T11 |
3161 |
|
T13 |
36 |
auto[1] |
auto[0] |
auto[1] |
1276557 |
1 |
|
|
T1 |
4138 |
|
T11 |
5384 |
|
T13 |
40 |
auto[1] |
auto[1] |
auto[0] |
1870786 |
1 |
|
|
T1 |
2227 |
|
T11 |
3572 |
|
T13 |
16 |
auto[1] |
auto[1] |
auto[1] |
1289597 |
1 |
|
|
T1 |
3921 |
|
T11 |
5916 |
|
T13 |
32 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |