Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8396175 |
1 |
|
|
T22 |
338 |
|
T1 |
13699 |
|
T11 |
24090 |
auto[1] |
6313320 |
1 |
|
|
T1 |
12666 |
|
T11 |
17504 |
|
T13 |
118 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12142563 |
1 |
|
|
T22 |
338 |
|
T1 |
18885 |
|
T11 |
29793 |
auto[1] |
2566932 |
1 |
|
|
T1 |
7480 |
|
T11 |
11801 |
|
T13 |
60 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8427955 |
1 |
|
|
T22 |
338 |
|
T1 |
14802 |
|
T11 |
22498 |
auto[1] |
6281540 |
1 |
|
|
T1 |
11563 |
|
T11 |
19096 |
|
T13 |
106 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1850701 |
1 |
|
|
T1 |
1859 |
|
T11 |
3766 |
|
T13 |
22 |
auto[1] |
auto[0] |
auto[1] |
1282203 |
1 |
|
|
T1 |
3204 |
|
T11 |
6309 |
|
T13 |
40 |
auto[1] |
auto[1] |
auto[0] |
1863907 |
1 |
|
|
T1 |
2224 |
|
T11 |
3529 |
|
T13 |
24 |
auto[1] |
auto[1] |
auto[1] |
1284729 |
1 |
|
|
T1 |
4276 |
|
T11 |
5492 |
|
T13 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |