Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8414767 |
1 |
|
|
T22 |
338 |
|
T1 |
15105 |
|
T11 |
21755 |
auto[1] |
6294728 |
1 |
|
|
T1 |
11260 |
|
T11 |
19839 |
|
T13 |
146 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12145442 |
1 |
|
|
T22 |
338 |
|
T1 |
18873 |
|
T11 |
29638 |
auto[1] |
2564053 |
1 |
|
|
T1 |
7492 |
|
T11 |
11956 |
|
T13 |
82 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8435219 |
1 |
|
|
T22 |
338 |
|
T1 |
14386 |
|
T11 |
22093 |
auto[1] |
6274276 |
1 |
|
|
T1 |
11979 |
|
T11 |
19501 |
|
T13 |
145 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1845639 |
1 |
|
|
T1 |
2351 |
|
T11 |
3613 |
|
T13 |
31 |
auto[1] |
auto[0] |
auto[1] |
1280009 |
1 |
|
|
T1 |
3852 |
|
T11 |
5297 |
|
T13 |
31 |
auto[1] |
auto[1] |
auto[0] |
1864584 |
1 |
|
|
T1 |
2136 |
|
T11 |
3932 |
|
T13 |
32 |
auto[1] |
auto[1] |
auto[1] |
1284044 |
1 |
|
|
T1 |
3640 |
|
T11 |
6659 |
|
T13 |
51 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |