Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8432975 |
1 |
|
|
T22 |
338 |
|
T1 |
15545 |
|
T11 |
22396 |
auto[1] |
6276520 |
1 |
|
|
T1 |
10820 |
|
T11 |
19198 |
|
T13 |
149 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12133021 |
1 |
|
|
T22 |
338 |
|
T1 |
18725 |
|
T11 |
29972 |
auto[1] |
2576474 |
1 |
|
|
T1 |
7640 |
|
T11 |
11622 |
|
T13 |
90 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8396950 |
1 |
|
|
T22 |
338 |
|
T1 |
14629 |
|
T11 |
23328 |
auto[1] |
6312545 |
1 |
|
|
T1 |
11736 |
|
T11 |
18266 |
|
T13 |
144 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1879271 |
1 |
|
|
T1 |
2320 |
|
T11 |
3297 |
|
T13 |
12 |
auto[1] |
auto[0] |
auto[1] |
1296677 |
1 |
|
|
T1 |
4228 |
|
T11 |
5430 |
|
T13 |
41 |
auto[1] |
auto[1] |
auto[0] |
1856800 |
1 |
|
|
T1 |
1776 |
|
T11 |
3347 |
|
T13 |
42 |
auto[1] |
auto[1] |
auto[1] |
1279797 |
1 |
|
|
T1 |
3412 |
|
T11 |
6192 |
|
T13 |
49 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |