Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8411720 |
1 |
|
|
T22 |
338 |
|
T1 |
13937 |
|
T11 |
22995 |
auto[1] |
6297775 |
1 |
|
|
T1 |
12428 |
|
T11 |
18599 |
|
T13 |
153 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12149909 |
1 |
|
|
T22 |
338 |
|
T1 |
19073 |
|
T11 |
30086 |
auto[1] |
2559586 |
1 |
|
|
T1 |
7292 |
|
T11 |
11508 |
|
T13 |
69 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8424900 |
1 |
|
|
T22 |
338 |
|
T1 |
15030 |
|
T11 |
22546 |
auto[1] |
6284595 |
1 |
|
|
T1 |
11335 |
|
T11 |
19048 |
|
T13 |
138 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1871716 |
1 |
|
|
T1 |
2039 |
|
T11 |
3824 |
|
T13 |
25 |
auto[1] |
auto[0] |
auto[1] |
1284496 |
1 |
|
|
T1 |
3507 |
|
T11 |
5668 |
|
T13 |
44 |
auto[1] |
auto[1] |
auto[0] |
1853293 |
1 |
|
|
T1 |
2004 |
|
T11 |
3716 |
|
T13 |
44 |
auto[1] |
auto[1] |
auto[1] |
1275090 |
1 |
|
|
T1 |
3785 |
|
T11 |
5840 |
|
T13 |
25 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |