Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8399096 |
1 |
|
|
T22 |
338 |
|
T1 |
15282 |
|
T11 |
23176 |
auto[1] |
6310399 |
1 |
|
|
T1 |
11083 |
|
T11 |
18418 |
|
T13 |
101 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12146923 |
1 |
|
|
T22 |
338 |
|
T1 |
18501 |
|
T11 |
30611 |
auto[1] |
2562572 |
1 |
|
|
T1 |
7864 |
|
T11 |
10983 |
|
T13 |
55 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8439108 |
1 |
|
|
T22 |
338 |
|
T1 |
13981 |
|
T11 |
23523 |
auto[1] |
6270387 |
1 |
|
|
T1 |
12384 |
|
T11 |
18071 |
|
T13 |
133 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1847063 |
1 |
|
|
T1 |
2479 |
|
T11 |
3366 |
|
T13 |
52 |
auto[1] |
auto[0] |
auto[1] |
1282722 |
1 |
|
|
T1 |
4421 |
|
T11 |
5250 |
|
T13 |
32 |
auto[1] |
auto[1] |
auto[0] |
1860752 |
1 |
|
|
T1 |
2041 |
|
T11 |
3722 |
|
T13 |
26 |
auto[1] |
auto[1] |
auto[1] |
1279850 |
1 |
|
|
T1 |
3443 |
|
T11 |
5733 |
|
T13 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |