Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8440956 |
1 |
|
|
T22 |
338 |
|
T1 |
14220 |
|
T11 |
22747 |
auto[1] |
6268539 |
1 |
|
|
T1 |
12145 |
|
T11 |
18847 |
|
T13 |
128 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12141239 |
1 |
|
|
T22 |
338 |
|
T1 |
19374 |
|
T11 |
29987 |
auto[1] |
2568256 |
1 |
|
|
T1 |
6991 |
|
T11 |
11607 |
|
T13 |
90 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8412568 |
1 |
|
|
T22 |
338 |
|
T1 |
15318 |
|
T11 |
22770 |
auto[1] |
6296927 |
1 |
|
|
T1 |
11047 |
|
T11 |
18824 |
|
T13 |
155 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1880611 |
1 |
|
|
T1 |
1849 |
|
T11 |
3730 |
|
T13 |
29 |
auto[1] |
auto[0] |
auto[1] |
1288243 |
1 |
|
|
T1 |
3355 |
|
T11 |
5963 |
|
T13 |
37 |
auto[1] |
auto[1] |
auto[0] |
1848060 |
1 |
|
|
T1 |
2207 |
|
T11 |
3487 |
|
T13 |
36 |
auto[1] |
auto[1] |
auto[1] |
1280013 |
1 |
|
|
T1 |
3636 |
|
T11 |
5644 |
|
T13 |
53 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |