Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8428142 |
1 |
|
|
T22 |
338 |
|
T1 |
14358 |
|
T11 |
22839 |
auto[1] |
6281353 |
1 |
|
|
T1 |
12007 |
|
T11 |
18755 |
|
T13 |
167 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12132288 |
1 |
|
|
T22 |
338 |
|
T1 |
18779 |
|
T11 |
30135 |
auto[1] |
2577207 |
1 |
|
|
T1 |
7586 |
|
T11 |
11459 |
|
T13 |
81 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8388473 |
1 |
|
|
T22 |
338 |
|
T1 |
14493 |
|
T11 |
23132 |
auto[1] |
6321022 |
1 |
|
|
T1 |
11872 |
|
T11 |
18462 |
|
T13 |
168 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1880001 |
1 |
|
|
T1 |
2086 |
|
T11 |
3516 |
|
T13 |
39 |
auto[1] |
auto[0] |
auto[1] |
1293986 |
1 |
|
|
T1 |
3741 |
|
T11 |
5764 |
|
T13 |
24 |
auto[1] |
auto[1] |
auto[0] |
1863814 |
1 |
|
|
T1 |
2200 |
|
T11 |
3487 |
|
T13 |
48 |
auto[1] |
auto[1] |
auto[1] |
1283221 |
1 |
|
|
T1 |
3845 |
|
T11 |
5695 |
|
T13 |
57 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |