Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8429522 |
1 |
|
|
T22 |
338 |
|
T1 |
14640 |
|
T11 |
21568 |
auto[1] |
6279973 |
1 |
|
|
T1 |
11725 |
|
T11 |
20026 |
|
T13 |
161 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12134716 |
1 |
|
|
T22 |
338 |
|
T1 |
19125 |
|
T11 |
29239 |
auto[1] |
2574779 |
1 |
|
|
T1 |
7240 |
|
T11 |
12355 |
|
T13 |
96 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8415805 |
1 |
|
|
T22 |
338 |
|
T1 |
15033 |
|
T11 |
21901 |
auto[1] |
6293690 |
1 |
|
|
T1 |
11332 |
|
T11 |
19693 |
|
T13 |
159 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1872117 |
1 |
|
|
T1 |
2106 |
|
T11 |
3428 |
|
T13 |
25 |
auto[1] |
auto[0] |
auto[1] |
1290232 |
1 |
|
|
T1 |
3583 |
|
T11 |
5370 |
|
T13 |
37 |
auto[1] |
auto[1] |
auto[0] |
1846794 |
1 |
|
|
T1 |
1986 |
|
T11 |
3910 |
|
T13 |
38 |
auto[1] |
auto[1] |
auto[1] |
1284547 |
1 |
|
|
T1 |
3657 |
|
T11 |
6985 |
|
T13 |
59 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |