Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8397988 |
1 |
|
|
T22 |
338 |
|
T1 |
14443 |
|
T11 |
22625 |
| auto[1] |
6311507 |
1 |
|
|
T1 |
11922 |
|
T11 |
18969 |
|
T13 |
107 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13903245 |
1 |
|
|
T22 |
338 |
|
T1 |
25204 |
|
T11 |
39230 |
| auto[1] |
806250 |
1 |
|
|
T1 |
1161 |
|
T11 |
2364 |
|
T13 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8424425 |
1 |
|
|
T22 |
338 |
|
T1 |
15487 |
|
T11 |
22991 |
| auto[1] |
6285070 |
1 |
|
|
T1 |
10878 |
|
T11 |
18603 |
|
T13 |
154 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2730736 |
1 |
|
|
T1 |
4637 |
|
T11 |
8418 |
|
T13 |
86 |
| auto[1] |
auto[0] |
auto[1] |
401421 |
1 |
|
|
T1 |
523 |
|
T11 |
1218 |
|
T13 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2748084 |
1 |
|
|
T1 |
5080 |
|
T11 |
7821 |
|
T13 |
59 |
| auto[1] |
auto[1] |
auto[1] |
404829 |
1 |
|
|
T1 |
638 |
|
T11 |
1146 |
|
T13 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |