Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.97


Total test records in report: 942
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T41 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3715126527 Jun 02 01:27:22 PM PDT 24 Jun 02 01:27:23 PM PDT 24 45860933 ps
T84 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2171172960 Jun 02 01:27:18 PM PDT 24 Jun 02 01:27:20 PM PDT 24 130446322 ps
T769 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1100935380 Jun 02 01:27:24 PM PDT 24 Jun 02 01:27:26 PM PDT 24 38683950 ps
T770 /workspace/coverage/cover_reg_top/6.gpio_intr_test.434967149 Jun 02 01:27:21 PM PDT 24 Jun 02 01:27:22 PM PDT 24 49007768 ps
T98 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1867645831 Jun 02 01:27:23 PM PDT 24 Jun 02 01:27:24 PM PDT 24 93597326 ps
T771 /workspace/coverage/cover_reg_top/48.gpio_intr_test.796585706 Jun 02 01:27:49 PM PDT 24 Jun 02 01:27:50 PM PDT 24 27333929 ps
T103 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.4257811503 Jun 02 01:27:28 PM PDT 24 Jun 02 01:27:30 PM PDT 24 48242078 ps
T772 /workspace/coverage/cover_reg_top/46.gpio_intr_test.2919967851 Jun 02 01:27:48 PM PDT 24 Jun 02 01:27:49 PM PDT 24 13519632 ps
T773 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2455337966 Jun 02 01:27:29 PM PDT 24 Jun 02 01:27:31 PM PDT 24 15173101 ps
T774 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3251868235 Jun 02 01:27:28 PM PDT 24 Jun 02 01:27:29 PM PDT 24 17839875 ps
T775 /workspace/coverage/cover_reg_top/32.gpio_intr_test.3819245567 Jun 02 01:27:42 PM PDT 24 Jun 02 01:27:43 PM PDT 24 25326641 ps
T776 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2412095782 Jun 02 01:27:18 PM PDT 24 Jun 02 01:27:21 PM PDT 24 174401910 ps
T777 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3868413824 Jun 02 01:27:17 PM PDT 24 Jun 02 01:27:18 PM PDT 24 14797677 ps
T778 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1461503884 Jun 02 01:27:37 PM PDT 24 Jun 02 01:27:38 PM PDT 24 81553454 ps
T779 /workspace/coverage/cover_reg_top/4.gpio_intr_test.2835761638 Jun 02 01:27:18 PM PDT 24 Jun 02 01:27:19 PM PDT 24 14910106 ps
T780 /workspace/coverage/cover_reg_top/31.gpio_intr_test.1978678867 Jun 02 01:27:42 PM PDT 24 Jun 02 01:27:43 PM PDT 24 25116416 ps
T85 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2395845262 Jun 02 01:27:23 PM PDT 24 Jun 02 01:27:24 PM PDT 24 44266673 ps
T781 /workspace/coverage/cover_reg_top/2.gpio_intr_test.2256874677 Jun 02 01:27:16 PM PDT 24 Jun 02 01:27:17 PM PDT 24 24241719 ps
T99 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.25770392 Jun 02 01:27:36 PM PDT 24 Jun 02 01:27:37 PM PDT 24 24795822 ps
T782 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.56811463 Jun 02 01:27:18 PM PDT 24 Jun 02 01:27:20 PM PDT 24 603573928 ps
T783 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3936391262 Jun 02 01:27:11 PM PDT 24 Jun 02 01:27:13 PM PDT 24 31855633 ps
T104 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1738801964 Jun 02 01:27:23 PM PDT 24 Jun 02 01:27:25 PM PDT 24 275509687 ps
T784 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4106459512 Jun 02 01:27:19 PM PDT 24 Jun 02 01:27:22 PM PDT 24 3378638867 ps
T785 /workspace/coverage/cover_reg_top/12.gpio_intr_test.3232470119 Jun 02 01:27:37 PM PDT 24 Jun 02 01:27:38 PM PDT 24 31710882 ps
T100 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3159453977 Jun 02 01:27:36 PM PDT 24 Jun 02 01:27:38 PM PDT 24 72036220 ps
T786 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3697630918 Jun 02 01:27:18 PM PDT 24 Jun 02 01:27:21 PM PDT 24 265805376 ps
T787 /workspace/coverage/cover_reg_top/16.gpio_intr_test.1233721691 Jun 02 01:27:40 PM PDT 24 Jun 02 01:27:41 PM PDT 24 15335734 ps
T788 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.984242115 Jun 02 01:27:35 PM PDT 24 Jun 02 01:27:37 PM PDT 24 25618250 ps
T789 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1656321510 Jun 02 01:27:44 PM PDT 24 Jun 02 01:27:45 PM PDT 24 60575380 ps
T790 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3316193826 Jun 02 01:27:09 PM PDT 24 Jun 02 01:27:11 PM PDT 24 44760966 ps
T791 /workspace/coverage/cover_reg_top/35.gpio_intr_test.1294135830 Jun 02 01:27:45 PM PDT 24 Jun 02 01:27:46 PM PDT 24 45860542 ps
T792 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2933067043 Jun 02 01:27:23 PM PDT 24 Jun 02 01:27:25 PM PDT 24 128217322 ps
T793 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1806058287 Jun 02 01:27:23 PM PDT 24 Jun 02 01:27:24 PM PDT 24 141966460 ps
T794 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2412339321 Jun 02 01:27:23 PM PDT 24 Jun 02 01:27:25 PM PDT 24 358298883 ps
T86 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.540915095 Jun 02 01:27:24 PM PDT 24 Jun 02 01:27:25 PM PDT 24 13076538 ps
T795 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3487672045 Jun 02 01:27:20 PM PDT 24 Jun 02 01:27:22 PM PDT 24 127162306 ps
T796 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3424009126 Jun 02 01:27:40 PM PDT 24 Jun 02 01:27:41 PM PDT 24 97034138 ps
T797 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.4094355130 Jun 02 01:27:16 PM PDT 24 Jun 02 01:27:17 PM PDT 24 20416210 ps
T798 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4014402673 Jun 02 01:27:18 PM PDT 24 Jun 02 01:27:19 PM PDT 24 17393274 ps
T799 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3049549260 Jun 02 01:27:37 PM PDT 24 Jun 02 01:27:38 PM PDT 24 41879606 ps
T800 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3118808127 Jun 02 01:27:36 PM PDT 24 Jun 02 01:27:37 PM PDT 24 60243314 ps
T801 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2427410825 Jun 02 01:27:36 PM PDT 24 Jun 02 01:27:38 PM PDT 24 13512998 ps
T802 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2829285895 Jun 02 01:27:37 PM PDT 24 Jun 02 01:27:39 PM PDT 24 96660468 ps
T803 /workspace/coverage/cover_reg_top/17.gpio_intr_test.70534412 Jun 02 01:27:37 PM PDT 24 Jun 02 01:27:38 PM PDT 24 15094573 ps
T804 /workspace/coverage/cover_reg_top/30.gpio_intr_test.4226350859 Jun 02 01:27:43 PM PDT 24 Jun 02 01:27:44 PM PDT 24 39238512 ps
T805 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.4139754542 Jun 02 01:27:11 PM PDT 24 Jun 02 01:27:12 PM PDT 24 87398291 ps
T806 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1651877415 Jun 02 01:27:25 PM PDT 24 Jun 02 01:27:26 PM PDT 24 20681436 ps
T807 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3050238835 Jun 02 01:27:44 PM PDT 24 Jun 02 01:27:45 PM PDT 24 44036441 ps
T87 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3829398513 Jun 02 01:27:09 PM PDT 24 Jun 02 01:27:10 PM PDT 24 16014285 ps
T808 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1607101725 Jun 02 01:27:31 PM PDT 24 Jun 02 01:27:32 PM PDT 24 42416864 ps
T809 /workspace/coverage/cover_reg_top/44.gpio_intr_test.172486525 Jun 02 01:27:49 PM PDT 24 Jun 02 01:27:50 PM PDT 24 44811997 ps
T810 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.147802101 Jun 02 01:27:36 PM PDT 24 Jun 02 01:27:37 PM PDT 24 13932115 ps
T811 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3468685907 Jun 02 01:27:37 PM PDT 24 Jun 02 01:27:40 PM PDT 24 808322177 ps
T812 /workspace/coverage/cover_reg_top/9.gpio_intr_test.4097746714 Jun 02 01:27:23 PM PDT 24 Jun 02 01:27:24 PM PDT 24 54488668 ps
T813 /workspace/coverage/cover_reg_top/25.gpio_intr_test.4185749320 Jun 02 01:27:42 PM PDT 24 Jun 02 01:27:43 PM PDT 24 20526866 ps
T814 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3523632504 Jun 02 01:27:22 PM PDT 24 Jun 02 01:27:23 PM PDT 24 35954008 ps
T815 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.747199838 Jun 02 01:27:23 PM PDT 24 Jun 02 01:27:26 PM PDT 24 122897715 ps
T88 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2418840238 Jun 02 01:27:15 PM PDT 24 Jun 02 01:27:16 PM PDT 24 27043827 ps
T816 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2177166660 Jun 02 01:27:32 PM PDT 24 Jun 02 01:27:34 PM PDT 24 43569603 ps
T817 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3778375462 Jun 02 01:27:41 PM PDT 24 Jun 02 01:27:43 PM PDT 24 95937324 ps
T89 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3692398951 Jun 02 01:27:24 PM PDT 24 Jun 02 01:27:26 PM PDT 24 33154986 ps
T105 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3571387020 Jun 02 01:27:21 PM PDT 24 Jun 02 01:27:23 PM PDT 24 246498930 ps
T818 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2912505405 Jun 02 01:27:10 PM PDT 24 Jun 02 01:27:11 PM PDT 24 33649122 ps
T819 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.424366829 Jun 02 01:27:19 PM PDT 24 Jun 02 01:27:21 PM PDT 24 185266292 ps
T820 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2783295418 Jun 02 01:27:37 PM PDT 24 Jun 02 01:27:39 PM PDT 24 386383198 ps
T39 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.855876480 Jun 02 01:27:36 PM PDT 24 Jun 02 01:27:38 PM PDT 24 123207404 ps
T821 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1271772010 Jun 02 01:27:12 PM PDT 24 Jun 02 01:27:13 PM PDT 24 52748604 ps
T822 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3151854049 Jun 02 01:27:23 PM PDT 24 Jun 02 01:27:24 PM PDT 24 161178410 ps
T823 /workspace/coverage/cover_reg_top/22.gpio_intr_test.3048103994 Jun 02 01:27:44 PM PDT 24 Jun 02 01:27:45 PM PDT 24 24135813 ps
T824 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2986312467 Jun 02 01:27:19 PM PDT 24 Jun 02 01:27:20 PM PDT 24 62126057 ps
T825 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1744017282 Jun 02 01:27:37 PM PDT 24 Jun 02 01:27:39 PM PDT 24 24445685 ps
T90 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1501144492 Jun 02 01:27:28 PM PDT 24 Jun 02 01:27:29 PM PDT 24 51630582 ps
T826 /workspace/coverage/cover_reg_top/13.gpio_intr_test.3136613568 Jun 02 01:27:29 PM PDT 24 Jun 02 01:27:30 PM PDT 24 33047278 ps
T91 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2261680055 Jun 02 01:27:36 PM PDT 24 Jun 02 01:27:38 PM PDT 24 11374125 ps
T827 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2808738200 Jun 02 01:27:22 PM PDT 24 Jun 02 01:27:23 PM PDT 24 21317829 ps
T828 /workspace/coverage/cover_reg_top/49.gpio_intr_test.1582062482 Jun 02 01:27:44 PM PDT 24 Jun 02 01:27:45 PM PDT 24 49238761 ps
T829 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1656791221 Jun 02 01:27:25 PM PDT 24 Jun 02 01:27:27 PM PDT 24 133752570 ps
T830 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.642637546 Jun 02 01:27:31 PM PDT 24 Jun 02 01:27:32 PM PDT 24 13808453 ps
T831 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.63439712 Jun 02 01:27:31 PM PDT 24 Jun 02 01:27:32 PM PDT 24 23474098 ps
T832 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3283777872 Jun 02 01:27:44 PM PDT 24 Jun 02 01:27:45 PM PDT 24 26285058 ps
T833 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.4012806909 Jun 02 01:27:16 PM PDT 24 Jun 02 01:27:18 PM PDT 24 870582375 ps
T834 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3928137298 Jun 02 01:27:17 PM PDT 24 Jun 02 01:27:18 PM PDT 24 49156961 ps
T835 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.185741836 Jun 02 01:27:31 PM PDT 24 Jun 02 01:27:33 PM PDT 24 67702174 ps
T836 /workspace/coverage/cover_reg_top/18.gpio_intr_test.3607503598 Jun 02 01:27:37 PM PDT 24 Jun 02 01:27:39 PM PDT 24 19936789 ps
T837 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3721779962 Jun 02 01:27:35 PM PDT 24 Jun 02 01:27:37 PM PDT 24 150388157 ps
T838 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3032080303 Jun 02 01:27:37 PM PDT 24 Jun 02 01:27:39 PM PDT 24 246525375 ps
T839 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1600570075 Jun 02 01:27:23 PM PDT 24 Jun 02 01:27:24 PM PDT 24 16068332 ps
T93 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3562265283 Jun 02 01:27:12 PM PDT 24 Jun 02 01:27:13 PM PDT 24 15703145 ps
T92 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1660570604 Jun 02 01:27:16 PM PDT 24 Jun 02 01:27:18 PM PDT 24 47912987 ps
T840 /workspace/coverage/cover_reg_top/24.gpio_intr_test.277419230 Jun 02 01:27:43 PM PDT 24 Jun 02 01:27:44 PM PDT 24 61360337 ps
T841 /workspace/coverage/cover_reg_top/27.gpio_intr_test.1902971262 Jun 02 01:27:44 PM PDT 24 Jun 02 01:27:45 PM PDT 24 16042886 ps
T842 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3810736205 Jun 02 01:27:30 PM PDT 24 Jun 02 01:27:31 PM PDT 24 89202078 ps
T843 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2984069510 Jun 02 01:41:56 PM PDT 24 Jun 02 01:41:58 PM PDT 24 187489933 ps
T844 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.11468009 Jun 02 01:42:10 PM PDT 24 Jun 02 01:42:11 PM PDT 24 53746362 ps
T845 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2684384074 Jun 02 01:41:40 PM PDT 24 Jun 02 01:41:42 PM PDT 24 48548470 ps
T846 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4024859948 Jun 02 01:41:58 PM PDT 24 Jun 02 01:41:59 PM PDT 24 29857572 ps
T847 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1208835617 Jun 02 01:41:53 PM PDT 24 Jun 02 01:41:55 PM PDT 24 92505195 ps
T848 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.850269103 Jun 02 01:41:51 PM PDT 24 Jun 02 01:41:53 PM PDT 24 614062950 ps
T849 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.778295992 Jun 02 01:41:47 PM PDT 24 Jun 02 01:41:49 PM PDT 24 208899562 ps
T850 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3440558515 Jun 02 01:41:53 PM PDT 24 Jun 02 01:41:55 PM PDT 24 231218335 ps
T851 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2118784428 Jun 02 01:41:51 PM PDT 24 Jun 02 01:41:53 PM PDT 24 62651355 ps
T852 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.842045814 Jun 02 01:42:05 PM PDT 24 Jun 02 01:42:07 PM PDT 24 43222602 ps
T853 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3905469467 Jun 02 01:42:04 PM PDT 24 Jun 02 01:42:05 PM PDT 24 44931203 ps
T854 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2254542393 Jun 02 01:41:57 PM PDT 24 Jun 02 01:41:59 PM PDT 24 126225660 ps
T855 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.4018204094 Jun 02 01:41:46 PM PDT 24 Jun 02 01:41:48 PM PDT 24 70605891 ps
T856 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.699824140 Jun 02 01:41:58 PM PDT 24 Jun 02 01:42:00 PM PDT 24 55587547 ps
T857 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3865398235 Jun 02 01:41:51 PM PDT 24 Jun 02 01:41:53 PM PDT 24 98355709 ps
T858 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3109604101 Jun 02 01:42:02 PM PDT 24 Jun 02 01:42:04 PM PDT 24 274812461 ps
T859 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2623740314 Jun 02 01:41:46 PM PDT 24 Jun 02 01:41:48 PM PDT 24 342513675 ps
T860 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1165243338 Jun 02 01:41:57 PM PDT 24 Jun 02 01:41:59 PM PDT 24 116936344 ps
T861 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.126478379 Jun 02 01:42:11 PM PDT 24 Jun 02 01:42:13 PM PDT 24 127387190 ps
T862 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1460785157 Jun 02 01:41:46 PM PDT 24 Jun 02 01:41:48 PM PDT 24 169555975 ps
T863 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3870679007 Jun 02 01:41:59 PM PDT 24 Jun 02 01:42:01 PM PDT 24 166493861 ps
T864 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2609272320 Jun 02 01:41:50 PM PDT 24 Jun 02 01:41:52 PM PDT 24 747478830 ps
T865 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.84487820 Jun 02 01:41:52 PM PDT 24 Jun 02 01:41:54 PM PDT 24 198143109 ps
T866 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3199529302 Jun 02 01:41:51 PM PDT 24 Jun 02 01:41:53 PM PDT 24 159773886 ps
T867 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3498747267 Jun 02 01:42:03 PM PDT 24 Jun 02 01:42:05 PM PDT 24 94740790 ps
T868 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.190953189 Jun 02 01:41:47 PM PDT 24 Jun 02 01:41:49 PM PDT 24 50457001 ps
T869 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.612884198 Jun 02 01:41:51 PM PDT 24 Jun 02 01:41:53 PM PDT 24 37593496 ps
T870 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2619581747 Jun 02 01:41:52 PM PDT 24 Jun 02 01:41:53 PM PDT 24 129354608 ps
T871 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2561547897 Jun 02 01:41:51 PM PDT 24 Jun 02 01:41:52 PM PDT 24 152206232 ps
T872 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2064332438 Jun 02 01:41:58 PM PDT 24 Jun 02 01:41:59 PM PDT 24 85123399 ps
T873 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3454608085 Jun 02 01:41:53 PM PDT 24 Jun 02 01:41:54 PM PDT 24 70128260 ps
T874 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.307407035 Jun 02 01:41:59 PM PDT 24 Jun 02 01:42:00 PM PDT 24 310116111 ps
T875 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3496021418 Jun 02 01:41:58 PM PDT 24 Jun 02 01:42:00 PM PDT 24 319451169 ps
T876 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.422927517 Jun 02 01:42:03 PM PDT 24 Jun 02 01:42:05 PM PDT 24 112035715 ps
T877 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1690895641 Jun 02 01:41:46 PM PDT 24 Jun 02 01:41:48 PM PDT 24 139271427 ps
T878 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1294847647 Jun 02 01:41:51 PM PDT 24 Jun 02 01:41:53 PM PDT 24 104562161 ps
T879 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.213619737 Jun 02 01:41:45 PM PDT 24 Jun 02 01:41:47 PM PDT 24 59786103 ps
T880 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4246870590 Jun 02 01:42:11 PM PDT 24 Jun 02 01:42:12 PM PDT 24 164940181 ps
T881 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1010862264 Jun 02 01:41:58 PM PDT 24 Jun 02 01:42:00 PM PDT 24 80850475 ps
T882 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.862111718 Jun 02 01:42:09 PM PDT 24 Jun 02 01:42:11 PM PDT 24 42596830 ps
T883 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1657627682 Jun 02 01:42:05 PM PDT 24 Jun 02 01:42:07 PM PDT 24 96547792 ps
T884 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1692162051 Jun 02 01:42:03 PM PDT 24 Jun 02 01:42:04 PM PDT 24 206444441 ps
T885 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2358169734 Jun 02 01:42:10 PM PDT 24 Jun 02 01:42:12 PM PDT 24 79732944 ps
T886 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.772872122 Jun 02 01:42:09 PM PDT 24 Jun 02 01:42:11 PM PDT 24 168994420 ps
T887 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3471825996 Jun 02 01:41:57 PM PDT 24 Jun 02 01:41:58 PM PDT 24 186303944 ps
T888 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2744699474 Jun 02 01:42:04 PM PDT 24 Jun 02 01:42:06 PM PDT 24 81726643 ps
T889 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2373801390 Jun 02 01:41:57 PM PDT 24 Jun 02 01:41:58 PM PDT 24 147506690 ps
T890 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1276516478 Jun 02 01:41:57 PM PDT 24 Jun 02 01:41:59 PM PDT 24 108075050 ps
T891 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3143919059 Jun 02 01:42:03 PM PDT 24 Jun 02 01:42:05 PM PDT 24 97080662 ps
T892 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3173317797 Jun 02 01:42:17 PM PDT 24 Jun 02 01:42:19 PM PDT 24 26431077 ps
T893 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3850140235 Jun 02 01:41:59 PM PDT 24 Jun 02 01:42:00 PM PDT 24 69551198 ps
T894 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3473308969 Jun 02 01:42:03 PM PDT 24 Jun 02 01:42:05 PM PDT 24 27658423 ps
T895 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1407570483 Jun 02 01:41:48 PM PDT 24 Jun 02 01:41:49 PM PDT 24 97001119 ps
T896 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3071200357 Jun 02 01:41:50 PM PDT 24 Jun 02 01:41:52 PM PDT 24 77152713 ps
T897 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1967220636 Jun 02 01:42:09 PM PDT 24 Jun 02 01:42:11 PM PDT 24 127087612 ps
T898 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2973359543 Jun 02 01:41:48 PM PDT 24 Jun 02 01:41:49 PM PDT 24 27279197 ps
T899 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2365741577 Jun 02 01:41:52 PM PDT 24 Jun 02 01:41:53 PM PDT 24 23057583 ps
T900 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3099819191 Jun 02 01:41:51 PM PDT 24 Jun 02 01:41:53 PM PDT 24 141602603 ps
T901 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.458761935 Jun 02 01:41:44 PM PDT 24 Jun 02 01:41:46 PM PDT 24 67316011 ps
T902 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.617367701 Jun 02 01:41:45 PM PDT 24 Jun 02 01:41:47 PM PDT 24 65627881 ps
T903 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.267478412 Jun 02 01:42:10 PM PDT 24 Jun 02 01:42:11 PM PDT 24 26298880 ps
T904 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.327111901 Jun 02 01:41:59 PM PDT 24 Jun 02 01:42:01 PM PDT 24 475927471 ps
T905 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.268130733 Jun 02 01:41:57 PM PDT 24 Jun 02 01:41:58 PM PDT 24 246041704 ps
T906 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1202192634 Jun 02 01:41:50 PM PDT 24 Jun 02 01:41:51 PM PDT 24 174880781 ps
T907 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1876700506 Jun 02 01:42:09 PM PDT 24 Jun 02 01:42:11 PM PDT 24 272839964 ps
T908 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1861314363 Jun 02 01:41:46 PM PDT 24 Jun 02 01:41:48 PM PDT 24 77830925 ps
T909 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2106594943 Jun 02 01:42:06 PM PDT 24 Jun 02 01:42:07 PM PDT 24 37703074 ps
T910 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.868679752 Jun 02 01:41:57 PM PDT 24 Jun 02 01:41:59 PM PDT 24 140713547 ps
T911 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1583412879 Jun 02 01:41:51 PM PDT 24 Jun 02 01:41:53 PM PDT 24 85378552 ps
T912 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3075989895 Jun 02 01:42:03 PM PDT 24 Jun 02 01:42:04 PM PDT 24 75998904 ps
T913 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2718466261 Jun 02 01:42:09 PM PDT 24 Jun 02 01:42:11 PM PDT 24 202214040 ps
T914 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.354560098 Jun 02 01:42:10 PM PDT 24 Jun 02 01:42:12 PM PDT 24 74590185 ps
T915 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2092952367 Jun 02 01:41:48 PM PDT 24 Jun 02 01:41:50 PM PDT 24 47531748 ps
T916 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3581781113 Jun 02 01:41:59 PM PDT 24 Jun 02 01:42:01 PM PDT 24 171850671 ps
T917 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2224764207 Jun 02 01:42:04 PM PDT 24 Jun 02 01:42:05 PM PDT 24 154586716 ps
T918 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4219622534 Jun 02 01:41:46 PM PDT 24 Jun 02 01:41:48 PM PDT 24 49099833 ps
T919 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2745670494 Jun 02 01:41:58 PM PDT 24 Jun 02 01:42:00 PM PDT 24 309446065 ps
T920 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1576794276 Jun 02 01:42:04 PM PDT 24 Jun 02 01:42:05 PM PDT 24 69111883 ps
T921 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4058393086 Jun 02 01:42:05 PM PDT 24 Jun 02 01:42:07 PM PDT 24 46424607 ps
T922 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3547968332 Jun 02 01:41:52 PM PDT 24 Jun 02 01:41:54 PM PDT 24 173978377 ps
T923 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2320765137 Jun 02 01:41:49 PM PDT 24 Jun 02 01:41:51 PM PDT 24 44709247 ps
T924 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3386826096 Jun 02 01:42:02 PM PDT 24 Jun 02 01:42:03 PM PDT 24 43927905 ps
T925 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.985616231 Jun 02 01:41:58 PM PDT 24 Jun 02 01:41:59 PM PDT 24 233696575 ps
T926 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.855842604 Jun 02 01:41:51 PM PDT 24 Jun 02 01:41:53 PM PDT 24 37495734 ps
T927 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2858926821 Jun 02 01:41:46 PM PDT 24 Jun 02 01:41:48 PM PDT 24 374392338 ps
T928 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.4186749898 Jun 02 01:41:59 PM PDT 24 Jun 02 01:42:00 PM PDT 24 135718224 ps
T929 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2498107705 Jun 02 01:41:51 PM PDT 24 Jun 02 01:41:53 PM PDT 24 38421487 ps
T930 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.735316606 Jun 02 01:42:05 PM PDT 24 Jun 02 01:42:07 PM PDT 24 74401564 ps
T931 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4132090058 Jun 02 01:42:09 PM PDT 24 Jun 02 01:42:11 PM PDT 24 304413504 ps
T932 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3004775173 Jun 02 01:42:04 PM PDT 24 Jun 02 01:42:05 PM PDT 24 122864436 ps
T933 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4023506147 Jun 02 01:42:05 PM PDT 24 Jun 02 01:42:07 PM PDT 24 80015250 ps
T934 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.840902695 Jun 02 01:41:46 PM PDT 24 Jun 02 01:41:48 PM PDT 24 91153377 ps
T935 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1180257604 Jun 02 01:41:47 PM PDT 24 Jun 02 01:41:49 PM PDT 24 49364589 ps
T936 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1706005300 Jun 02 01:42:05 PM PDT 24 Jun 02 01:42:07 PM PDT 24 230901112 ps
T937 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.430658684 Jun 02 01:42:02 PM PDT 24 Jun 02 01:42:04 PM PDT 24 140853710 ps
T938 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.4081450321 Jun 02 01:41:51 PM PDT 24 Jun 02 01:41:53 PM PDT 24 45389209 ps
T939 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2169335390 Jun 02 01:41:58 PM PDT 24 Jun 02 01:42:00 PM PDT 24 81163462 ps
T940 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1251257317 Jun 02 01:41:52 PM PDT 24 Jun 02 01:41:53 PM PDT 24 505831100 ps
T941 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4019231561 Jun 02 01:42:09 PM PDT 24 Jun 02 01:42:11 PM PDT 24 55601649 ps
T942 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3366968950 Jun 02 01:41:47 PM PDT 24 Jun 02 01:41:49 PM PDT 24 80990419 ps

Test location /workspace/coverage/default/18.gpio_stress_all.60064373
Short name T1
Test name
Test status
Simulation time 4698856907 ps
CPU time 52.1 seconds
Started Jun 02 01:43:08 PM PDT 24
Finished Jun 02 01:44:01 PM PDT 24
Peak memory 198384 kb
Host smart-bd0b7c72-a3ee-4828-973c-0619d8b9c839
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60064373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gp
io_stress_all.60064373
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.140392303
Short name T106
Test name
Test status
Simulation time 35452194 ps
CPU time 1.57 seconds
Started Jun 02 01:42:45 PM PDT 24
Finished Jun 02 01:42:47 PM PDT 24
Peak memory 196832 kb
Host smart-279a71ce-608e-48b3-bb12-0b6bbded988a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140392303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.140392303
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1871816231
Short name T111
Test name
Test status
Simulation time 17461095770 ps
CPU time 125.3 seconds
Started Jun 02 01:43:32 PM PDT 24
Finished Jun 02 01:45:38 PM PDT 24
Peak memory 198004 kb
Host smart-4c5ca5f9-f68c-42d1-863b-f692ddd16e00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871816231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1871816231
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.2628322022
Short name T28
Test name
Test status
Simulation time 107556133644 ps
CPU time 1370.86 seconds
Started Jun 02 01:42:29 PM PDT 24
Finished Jun 02 02:05:20 PM PDT 24
Peak memory 198168 kb
Host smart-01029ef6-4571-411c-8955-3d3007e411d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2628322022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.2628322022
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.406465109
Short name T40
Test name
Test status
Simulation time 199338709 ps
CPU time 1.41 seconds
Started Jun 02 01:27:36 PM PDT 24
Finished Jun 02 01:27:38 PM PDT 24
Peak memory 197952 kb
Host smart-682e43b3-777b-4ac1-a7f2-73a3e5da4f3e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406465109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.406465109
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3145935701
Short name T176
Test name
Test status
Simulation time 40090887 ps
CPU time 0.58 seconds
Started Jun 02 01:42:55 PM PDT 24
Finished Jun 02 01:42:56 PM PDT 24
Peak memory 194052 kb
Host smart-2a1f34ba-e34b-4c43-b3c2-f934ad890e7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145935701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3145935701
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3863716853
Short name T35
Test name
Test status
Simulation time 36994855 ps
CPU time 0.78 seconds
Started Jun 02 01:42:16 PM PDT 24
Finished Jun 02 01:42:17 PM PDT 24
Peak memory 213648 kb
Host smart-a0d7fd2b-4a3a-49f0-8e1b-9f66b1ee30e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863716853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3863716853
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2261680055
Short name T91
Test name
Test status
Simulation time 11374125 ps
CPU time 0.6 seconds
Started Jun 02 01:27:36 PM PDT 24
Finished Jun 02 01:27:38 PM PDT 24
Peak memory 195320 kb
Host smart-c006d038-1079-4346-8836-119b08f79ee6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261680055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2261680055
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1867645831
Short name T98
Test name
Test status
Simulation time 93597326 ps
CPU time 0.76 seconds
Started Jun 02 01:27:23 PM PDT 24
Finished Jun 02 01:27:24 PM PDT 24
Peak memory 195056 kb
Host smart-3bccf13f-e2ca-43cc-9b4a-97cfd2207afa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867645831 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1867645831
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.915770036
Short name T38
Test name
Test status
Simulation time 388136617 ps
CPU time 1.46 seconds
Started Jun 02 01:27:24 PM PDT 24
Finished Jun 02 01:27:26 PM PDT 24
Peak memory 197076 kb
Host smart-c0af84c9-e7d8-40e6-b03b-560e01ddb97e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915770036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.915770036
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.4257811503
Short name T103
Test name
Test status
Simulation time 48242078 ps
CPU time 0.89 seconds
Started Jun 02 01:27:28 PM PDT 24
Finished Jun 02 01:27:30 PM PDT 24
Peak memory 197688 kb
Host smart-1005d3ba-571a-47f8-85e7-ebae83261629
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257811503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.4257811503
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3562265283
Short name T93
Test name
Test status
Simulation time 15703145 ps
CPU time 0.75 seconds
Started Jun 02 01:27:12 PM PDT 24
Finished Jun 02 01:27:13 PM PDT 24
Peak memory 195852 kb
Host smart-764042e6-f9e2-48ba-bfa2-02dc46725170
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562265283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3562265283
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.980667583
Short name T751
Test name
Test status
Simulation time 174292597 ps
CPU time 2.33 seconds
Started Jun 02 01:27:09 PM PDT 24
Finished Jun 02 01:27:12 PM PDT 24
Peak memory 196548 kb
Host smart-7f9f71b2-fbad-484a-bcf4-f53f28f3c880
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980667583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.980667583
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3829398513
Short name T87
Test name
Test status
Simulation time 16014285 ps
CPU time 0.63 seconds
Started Jun 02 01:27:09 PM PDT 24
Finished Jun 02 01:27:10 PM PDT 24
Peak memory 194196 kb
Host smart-68ad9a08-91da-4ce6-b207-17967df8eb09
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829398513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3829398513
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3804868897
Short name T726
Test name
Test status
Simulation time 17052713 ps
CPU time 0.88 seconds
Started Jun 02 01:27:10 PM PDT 24
Finished Jun 02 01:27:12 PM PDT 24
Peak memory 197860 kb
Host smart-e4055a43-eaf5-40aa-98a5-4306cb9c9830
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804868897 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3804868897
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2493009700
Short name T754
Test name
Test status
Simulation time 34635493 ps
CPU time 0.64 seconds
Started Jun 02 01:27:10 PM PDT 24
Finished Jun 02 01:27:11 PM PDT 24
Peak memory 195472 kb
Host smart-8bc11c7d-4c75-4055-a63e-75f3d055c0d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493009700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2493009700
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3802994008
Short name T767
Test name
Test status
Simulation time 30154431 ps
CPU time 0.57 seconds
Started Jun 02 01:27:09 PM PDT 24
Finished Jun 02 01:27:10 PM PDT 24
Peak memory 193568 kb
Host smart-060c1673-4ca2-4aa2-8b47-cb31227093aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802994008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3802994008
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3316193826
Short name T790
Test name
Test status
Simulation time 44760966 ps
CPU time 0.65 seconds
Started Jun 02 01:27:09 PM PDT 24
Finished Jun 02 01:27:11 PM PDT 24
Peak memory 195360 kb
Host smart-d18d9c07-c0d8-4e16-9de2-e1a913b19611
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316193826 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3316193826
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2720772886
Short name T736
Test name
Test status
Simulation time 82448503 ps
CPU time 1.52 seconds
Started Jun 02 01:27:11 PM PDT 24
Finished Jun 02 01:27:13 PM PDT 24
Peak memory 197924 kb
Host smart-164ab67e-d571-4a8a-8c9f-a1fbe0a58ebb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720772886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2720772886
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.351559487
Short name T31
Test name
Test status
Simulation time 159658281 ps
CPU time 0.87 seconds
Started Jun 02 01:27:10 PM PDT 24
Finished Jun 02 01:27:11 PM PDT 24
Peak memory 197228 kb
Host smart-3e23701b-ebc9-4c57-8148-2e7a9ec8b3e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351559487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.351559487
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2127502423
Short name T78
Test name
Test status
Simulation time 31245473 ps
CPU time 0.66 seconds
Started Jun 02 01:27:11 PM PDT 24
Finished Jun 02 01:27:12 PM PDT 24
Peak memory 194696 kb
Host smart-54f91e07-fbff-42aa-a33f-50d67ade855a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127502423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2127502423
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3697630918
Short name T786
Test name
Test status
Simulation time 265805376 ps
CPU time 2.34 seconds
Started Jun 02 01:27:18 PM PDT 24
Finished Jun 02 01:27:21 PM PDT 24
Peak memory 196464 kb
Host smart-94df19cf-1ac1-40d6-8a97-76aa59e9c9b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697630918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3697630918
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3941656346
Short name T79
Test name
Test status
Simulation time 43831770 ps
CPU time 0.61 seconds
Started Jun 02 01:27:15 PM PDT 24
Finished Jun 02 01:27:16 PM PDT 24
Peak memory 194712 kb
Host smart-44aa163b-ee9f-48c7-9007-bc046d78cff7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941656346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3941656346
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1966744957
Short name T733
Test name
Test status
Simulation time 275712775 ps
CPU time 1.16 seconds
Started Jun 02 01:27:09 PM PDT 24
Finished Jun 02 01:27:11 PM PDT 24
Peak memory 198024 kb
Host smart-88ea793f-ead9-44ce-bfa2-a3ecdfad8818
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966744957 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1966744957
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.4139754542
Short name T805
Test name
Test status
Simulation time 87398291 ps
CPU time 0.62 seconds
Started Jun 02 01:27:11 PM PDT 24
Finished Jun 02 01:27:12 PM PDT 24
Peak memory 195240 kb
Host smart-04cb408e-59ff-4329-95e9-59882715a614
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139754542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.4139754542
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2635899997
Short name T761
Test name
Test status
Simulation time 12317733 ps
CPU time 0.61 seconds
Started Jun 02 01:27:10 PM PDT 24
Finished Jun 02 01:27:11 PM PDT 24
Peak memory 193620 kb
Host smart-ff8e02cd-db2e-4d23-8923-02652bf3d215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635899997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2635899997
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2912505405
Short name T818
Test name
Test status
Simulation time 33649122 ps
CPU time 0.67 seconds
Started Jun 02 01:27:10 PM PDT 24
Finished Jun 02 01:27:11 PM PDT 24
Peak memory 195072 kb
Host smart-ad61765f-64a5-4f68-959f-798229e60f60
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912505405 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2912505405
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3936391262
Short name T783
Test name
Test status
Simulation time 31855633 ps
CPU time 1.62 seconds
Started Jun 02 01:27:11 PM PDT 24
Finished Jun 02 01:27:13 PM PDT 24
Peak memory 197956 kb
Host smart-955950c6-0fd8-4179-8a36-ae4fbed77536
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936391262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3936391262
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1271772010
Short name T821
Test name
Test status
Simulation time 52748604 ps
CPU time 0.83 seconds
Started Jun 02 01:27:12 PM PDT 24
Finished Jun 02 01:27:13 PM PDT 24
Peak memory 197008 kb
Host smart-801b9c66-2743-4839-b2c5-4c068578cbf3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271772010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1271772010
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1848531098
Short name T729
Test name
Test status
Simulation time 35687752 ps
CPU time 0.89 seconds
Started Jun 02 01:27:24 PM PDT 24
Finished Jun 02 01:27:26 PM PDT 24
Peak memory 197920 kb
Host smart-ad1640ba-81d6-4f3f-89e1-bef34139f162
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848531098 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1848531098
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.126463032
Short name T750
Test name
Test status
Simulation time 14142432 ps
CPU time 0.6 seconds
Started Jun 02 01:27:22 PM PDT 24
Finished Jun 02 01:27:24 PM PDT 24
Peak memory 195360 kb
Host smart-3d470b99-9da1-413f-b834-c6ff4dae4c4c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126463032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.126463032
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2953293401
Short name T717
Test name
Test status
Simulation time 222216953 ps
CPU time 0.63 seconds
Started Jun 02 01:27:35 PM PDT 24
Finished Jun 02 01:27:36 PM PDT 24
Peak memory 193572 kb
Host smart-86ba46ce-d13b-45a1-a06c-de5853966af9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953293401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2953293401
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3487672045
Short name T795
Test name
Test status
Simulation time 127162306 ps
CPU time 1.87 seconds
Started Jun 02 01:27:20 PM PDT 24
Finished Jun 02 01:27:22 PM PDT 24
Peak memory 197908 kb
Host smart-d1699c5f-f578-486b-8bb0-3322cce4696f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487672045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3487672045
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.496957427
Short name T765
Test name
Test status
Simulation time 39030817 ps
CPU time 0.9 seconds
Started Jun 02 01:27:30 PM PDT 24
Finished Jun 02 01:27:31 PM PDT 24
Peak memory 197920 kb
Host smart-dadc5627-2d1c-4fa2-b120-2390e74f7d30
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496957427 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.496957427
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.63439712
Short name T831
Test name
Test status
Simulation time 23474098 ps
CPU time 0.62 seconds
Started Jun 02 01:27:31 PM PDT 24
Finished Jun 02 01:27:32 PM PDT 24
Peak memory 195436 kb
Host smart-172cf1c5-f8af-4dc0-b7fb-4043d2682abf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63439712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_
csr_rw.63439712
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.881377433
Short name T762
Test name
Test status
Simulation time 115135401 ps
CPU time 0.61 seconds
Started Jun 02 01:27:34 PM PDT 24
Finished Jun 02 01:27:35 PM PDT 24
Peak memory 193580 kb
Host smart-56956608-50ae-4ae4-9edf-1a74617e6335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881377433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.881377433
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3159453977
Short name T100
Test name
Test status
Simulation time 72036220 ps
CPU time 0.85 seconds
Started Jun 02 01:27:36 PM PDT 24
Finished Jun 02 01:27:38 PM PDT 24
Peak memory 196108 kb
Host smart-d61a31b8-b3bd-4748-92ce-e2e1fda18f6b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159453977 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3159453977
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.106211277
Short name T753
Test name
Test status
Simulation time 162675130 ps
CPU time 2.29 seconds
Started Jun 02 01:27:29 PM PDT 24
Finished Jun 02 01:27:32 PM PDT 24
Peak memory 198008 kb
Host smart-75d9b3e1-e0dc-4d4f-8a20-d9a6b6ed523b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106211277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.106211277
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3049549260
Short name T799
Test name
Test status
Simulation time 41879606 ps
CPU time 0.98 seconds
Started Jun 02 01:27:37 PM PDT 24
Finished Jun 02 01:27:38 PM PDT 24
Peak memory 197820 kb
Host smart-14af51b2-ea25-4d16-8a92-f504128775ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049549260 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3049549260
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.642637546
Short name T830
Test name
Test status
Simulation time 13808453 ps
CPU time 0.66 seconds
Started Jun 02 01:27:31 PM PDT 24
Finished Jun 02 01:27:32 PM PDT 24
Peak memory 194692 kb
Host smart-33918ca9-3349-4fa6-999f-b6a87bda07a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642637546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.642637546
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3232470119
Short name T785
Test name
Test status
Simulation time 31710882 ps
CPU time 0.58 seconds
Started Jun 02 01:27:37 PM PDT 24
Finished Jun 02 01:27:38 PM PDT 24
Peak memory 194176 kb
Host smart-6a40d071-492e-42fe-8b82-77bb8ffe696b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232470119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3232470119
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.746296818
Short name T96
Test name
Test status
Simulation time 94012001 ps
CPU time 0.82 seconds
Started Jun 02 01:27:35 PM PDT 24
Finished Jun 02 01:27:36 PM PDT 24
Peak memory 196252 kb
Host smart-f3324a83-8511-41e6-9843-f604399d626e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746296818 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 12.gpio_same_csr_outstanding.746296818
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2652954497
Short name T745
Test name
Test status
Simulation time 518508440 ps
CPU time 2.53 seconds
Started Jun 02 01:27:28 PM PDT 24
Finished Jun 02 01:27:31 PM PDT 24
Peak memory 198052 kb
Host smart-36295432-9ee5-400a-8113-a2d6a110f535
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652954497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2652954497
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.844330965
Short name T32
Test name
Test status
Simulation time 45932585 ps
CPU time 0.91 seconds
Started Jun 02 01:27:30 PM PDT 24
Finished Jun 02 01:27:31 PM PDT 24
Peak memory 197744 kb
Host smart-3e9030ea-df4c-4412-a173-6860c214d2f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844330965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.844330965
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2829285895
Short name T802
Test name
Test status
Simulation time 96660468 ps
CPU time 0.95 seconds
Started Jun 02 01:27:37 PM PDT 24
Finished Jun 02 01:27:39 PM PDT 24
Peak memory 197876 kb
Host smart-1b82bb3e-6ad0-4478-9e95-90aa7babf143
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829285895 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2829285895
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1501144492
Short name T90
Test name
Test status
Simulation time 51630582 ps
CPU time 0.61 seconds
Started Jun 02 01:27:28 PM PDT 24
Finished Jun 02 01:27:29 PM PDT 24
Peak memory 194496 kb
Host smart-18d0b467-acee-444b-8641-ac176984ef17
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501144492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1501144492
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3136613568
Short name T826
Test name
Test status
Simulation time 33047278 ps
CPU time 0.6 seconds
Started Jun 02 01:27:29 PM PDT 24
Finished Jun 02 01:27:30 PM PDT 24
Peak memory 193620 kb
Host smart-a220a641-7b01-4619-a93c-e6ac81949908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136613568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3136613568
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3032080303
Short name T838
Test name
Test status
Simulation time 246525375 ps
CPU time 0.78 seconds
Started Jun 02 01:27:37 PM PDT 24
Finished Jun 02 01:27:39 PM PDT 24
Peak memory 196100 kb
Host smart-bfd2387f-9dec-4969-81a9-78dc928da5bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032080303 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3032080303
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.185741836
Short name T835
Test name
Test status
Simulation time 67702174 ps
CPU time 1.61 seconds
Started Jun 02 01:27:31 PM PDT 24
Finished Jun 02 01:27:33 PM PDT 24
Peak memory 197892 kb
Host smart-0c03bc03-22de-4a42-a34a-ff11bfa798dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185741836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.185741836
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2454073805
Short name T102
Test name
Test status
Simulation time 43319439 ps
CPU time 0.87 seconds
Started Jun 02 01:27:30 PM PDT 24
Finished Jun 02 01:27:31 PM PDT 24
Peak memory 197184 kb
Host smart-e444c230-b867-45b7-b7bb-33c42eceb67e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454073805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2454073805
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2177166660
Short name T816
Test name
Test status
Simulation time 43569603 ps
CPU time 1.1 seconds
Started Jun 02 01:27:32 PM PDT 24
Finished Jun 02 01:27:34 PM PDT 24
Peak memory 198080 kb
Host smart-cdaded3d-171a-4e1e-a833-e8823902e624
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177166660 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.2177166660
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2455337966
Short name T773
Test name
Test status
Simulation time 15173101 ps
CPU time 0.61 seconds
Started Jun 02 01:27:29 PM PDT 24
Finished Jun 02 01:27:31 PM PDT 24
Peak memory 194548 kb
Host smart-2726baa7-18c1-46ca-96b2-fcbe26513825
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455337966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2455337966
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.466469841
Short name T749
Test name
Test status
Simulation time 13665729 ps
CPU time 0.62 seconds
Started Jun 02 01:27:34 PM PDT 24
Finished Jun 02 01:27:35 PM PDT 24
Peak memory 193628 kb
Host smart-d7df9cdd-ab81-4b90-bc7a-a9b84ae58e4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466469841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.466469841
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1607101725
Short name T808
Test name
Test status
Simulation time 42416864 ps
CPU time 0.62 seconds
Started Jun 02 01:27:31 PM PDT 24
Finished Jun 02 01:27:32 PM PDT 24
Peak memory 195320 kb
Host smart-68f2cfb3-1843-4202-96ea-d053cb88f2fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607101725 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1607101725
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2453798846
Short name T728
Test name
Test status
Simulation time 21606474 ps
CPU time 1.04 seconds
Started Jun 02 01:27:32 PM PDT 24
Finished Jun 02 01:27:33 PM PDT 24
Peak memory 197964 kb
Host smart-a1398c7e-3cb9-48ba-be46-5d6a9877e35e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453798846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2453798846
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2447335977
Short name T42
Test name
Test status
Simulation time 80510540 ps
CPU time 1.16 seconds
Started Jun 02 01:27:30 PM PDT 24
Finished Jun 02 01:27:32 PM PDT 24
Peak memory 197936 kb
Host smart-d8f97c2c-f1a0-4d7f-8bdc-073186e34505
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447335977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2447335977
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.4261014514
Short name T752
Test name
Test status
Simulation time 113309065 ps
CPU time 0.83 seconds
Started Jun 02 01:27:29 PM PDT 24
Finished Jun 02 01:27:30 PM PDT 24
Peak memory 198156 kb
Host smart-0acd361e-268e-47a5-bc55-c6cf1b37ac3e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261014514 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.4261014514
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3810736205
Short name T842
Test name
Test status
Simulation time 89202078 ps
CPU time 0.56 seconds
Started Jun 02 01:27:30 PM PDT 24
Finished Jun 02 01:27:31 PM PDT 24
Peak memory 194468 kb
Host smart-3eec6f56-c832-4634-ab38-b7cf03c2373e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810736205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3810736205
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3251868235
Short name T774
Test name
Test status
Simulation time 17839875 ps
CPU time 0.62 seconds
Started Jun 02 01:27:28 PM PDT 24
Finished Jun 02 01:27:29 PM PDT 24
Peak memory 193668 kb
Host smart-1e4b3cbd-cf6e-4dfb-a0dc-b31398d64356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251868235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3251868235
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.342067193
Short name T76
Test name
Test status
Simulation time 19665117 ps
CPU time 0.64 seconds
Started Jun 02 01:27:32 PM PDT 24
Finished Jun 02 01:27:33 PM PDT 24
Peak memory 194760 kb
Host smart-2f874ed8-2a53-45f7-9ceb-81ea8da1d42b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342067193 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.342067193
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.550202184
Short name T764
Test name
Test status
Simulation time 115517878 ps
CPU time 1.41 seconds
Started Jun 02 01:27:30 PM PDT 24
Finished Jun 02 01:27:32 PM PDT 24
Peak memory 197944 kb
Host smart-041bdbdb-b358-4e73-a2a4-39bde032e610
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550202184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.550202184
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2783295418
Short name T820
Test name
Test status
Simulation time 386383198 ps
CPU time 1.14 seconds
Started Jun 02 01:27:37 PM PDT 24
Finished Jun 02 01:27:39 PM PDT 24
Peak memory 197896 kb
Host smart-0adc1a81-8321-4ba8-8943-a0069cf079b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783295418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2783295418
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.551501106
Short name T760
Test name
Test status
Simulation time 49655038 ps
CPU time 1.44 seconds
Started Jun 02 01:27:36 PM PDT 24
Finished Jun 02 01:27:38 PM PDT 24
Peak memory 198000 kb
Host smart-79bf45db-41fc-4b16-b809-a1dd2f7a9149
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551501106 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.551501106
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.147802101
Short name T810
Test name
Test status
Simulation time 13932115 ps
CPU time 0.62 seconds
Started Jun 02 01:27:36 PM PDT 24
Finished Jun 02 01:27:37 PM PDT 24
Peak memory 194636 kb
Host smart-d90376fa-2cc3-431a-8415-80c8a2324f21
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147802101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.147802101
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1233721691
Short name T787
Test name
Test status
Simulation time 15335734 ps
CPU time 0.59 seconds
Started Jun 02 01:27:40 PM PDT 24
Finished Jun 02 01:27:41 PM PDT 24
Peak memory 193540 kb
Host smart-918f2c64-3cff-4485-8e65-49a361d984a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233721691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1233721691
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2348422583
Short name T81
Test name
Test status
Simulation time 38387688 ps
CPU time 0.83 seconds
Started Jun 02 01:27:29 PM PDT 24
Finished Jun 02 01:27:31 PM PDT 24
Peak memory 196936 kb
Host smart-35932ecb-cf91-4f4d-9e29-88aad0d3db57
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348422583 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2348422583
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.984242115
Short name T788
Test name
Test status
Simulation time 25618250 ps
CPU time 1.31 seconds
Started Jun 02 01:27:35 PM PDT 24
Finished Jun 02 01:27:37 PM PDT 24
Peak memory 197936 kb
Host smart-8badc13b-062a-471f-8be0-2508d1a6ffa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984242115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.984242115
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.4043295328
Short name T718
Test name
Test status
Simulation time 57687000 ps
CPU time 1.16 seconds
Started Jun 02 01:27:35 PM PDT 24
Finished Jun 02 01:27:37 PM PDT 24
Peak memory 198016 kb
Host smart-adff1a80-6e14-444d-b7e8-015ad8019553
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043295328 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.4043295328
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.70534412
Short name T803
Test name
Test status
Simulation time 15094573 ps
CPU time 0.59 seconds
Started Jun 02 01:27:37 PM PDT 24
Finished Jun 02 01:27:38 PM PDT 24
Peak memory 193492 kb
Host smart-59a3f642-aa57-4722-b781-2af484d05e5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70534412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.70534412
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3424009126
Short name T796
Test name
Test status
Simulation time 97034138 ps
CPU time 0.73 seconds
Started Jun 02 01:27:40 PM PDT 24
Finished Jun 02 01:27:41 PM PDT 24
Peak memory 195984 kb
Host smart-3fad98ce-c7f9-4827-92e2-dfc323edc17d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424009126 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3424009126
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3468685907
Short name T811
Test name
Test status
Simulation time 808322177 ps
CPU time 2.33 seconds
Started Jun 02 01:27:37 PM PDT 24
Finished Jun 02 01:27:40 PM PDT 24
Peak memory 197892 kb
Host smart-2801d0a1-b061-4432-8af3-30170ddcd3b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468685907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3468685907
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.855876480
Short name T39
Test name
Test status
Simulation time 123207404 ps
CPU time 1.47 seconds
Started Jun 02 01:27:36 PM PDT 24
Finished Jun 02 01:27:38 PM PDT 24
Peak memory 198120 kb
Host smart-7e0dc744-e14d-4f08-bd5c-a08b91152c97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855876480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.855876480
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3118808127
Short name T800
Test name
Test status
Simulation time 60243314 ps
CPU time 0.9 seconds
Started Jun 02 01:27:36 PM PDT 24
Finished Jun 02 01:27:37 PM PDT 24
Peak memory 197852 kb
Host smart-2052b82b-a638-4c0c-a2cd-bbc6117242ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118808127 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3118808127
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1461503884
Short name T778
Test name
Test status
Simulation time 81553454 ps
CPU time 0.62 seconds
Started Jun 02 01:27:37 PM PDT 24
Finished Jun 02 01:27:38 PM PDT 24
Peak memory 194692 kb
Host smart-d00428c2-10f5-4f80-ae09-50c568318847
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461503884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1461503884
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3607503598
Short name T836
Test name
Test status
Simulation time 19936789 ps
CPU time 0.64 seconds
Started Jun 02 01:27:37 PM PDT 24
Finished Jun 02 01:27:39 PM PDT 24
Peak memory 193656 kb
Host smart-118f62b9-c6da-4f7a-aca8-d3cc5e5e90f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607503598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3607503598
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2427410825
Short name T801
Test name
Test status
Simulation time 13512998 ps
CPU time 0.69 seconds
Started Jun 02 01:27:36 PM PDT 24
Finished Jun 02 01:27:38 PM PDT 24
Peak memory 194944 kb
Host smart-de14dbc5-0445-4e6e-89a4-e685658f93ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427410825 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2427410825
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1577725992
Short name T730
Test name
Test status
Simulation time 250900937 ps
CPU time 1.7 seconds
Started Jun 02 01:27:36 PM PDT 24
Finished Jun 02 01:27:38 PM PDT 24
Peak memory 197948 kb
Host smart-77c9ee02-68bd-450c-81b2-a4c78cb02aee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577725992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1577725992
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1272575725
Short name T756
Test name
Test status
Simulation time 43116090 ps
CPU time 0.91 seconds
Started Jun 02 01:27:35 PM PDT 24
Finished Jun 02 01:27:37 PM PDT 24
Peak memory 197060 kb
Host smart-80863233-6040-4e52-8ef8-3414d8629d2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272575725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1272575725
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3721779962
Short name T837
Test name
Test status
Simulation time 150388157 ps
CPU time 0.94 seconds
Started Jun 02 01:27:35 PM PDT 24
Finished Jun 02 01:27:37 PM PDT 24
Peak memory 197852 kb
Host smart-7aea1917-4332-4b41-9508-c06ec5d55833
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721779962 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3721779962
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2978850471
Short name T77
Test name
Test status
Simulation time 56275797 ps
CPU time 0.61 seconds
Started Jun 02 01:27:39 PM PDT 24
Finished Jun 02 01:27:40 PM PDT 24
Peak memory 194740 kb
Host smart-1b88c913-821a-4eab-a66e-bc1ea2888192
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978850471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2978850471
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.654622741
Short name T727
Test name
Test status
Simulation time 18081984 ps
CPU time 0.61 seconds
Started Jun 02 01:27:35 PM PDT 24
Finished Jun 02 01:27:36 PM PDT 24
Peak memory 193624 kb
Host smart-1c59646b-9c9f-4705-b4ea-b97d10271709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654622741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.654622741
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.25770392
Short name T99
Test name
Test status
Simulation time 24795822 ps
CPU time 0.71 seconds
Started Jun 02 01:27:36 PM PDT 24
Finished Jun 02 01:27:37 PM PDT 24
Peak memory 195408 kb
Host smart-fce49a5c-f85e-4c24-b3ee-987ee3afe459
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25770392 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.gpio_same_csr_outstanding.25770392
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1744017282
Short name T825
Test name
Test status
Simulation time 24445685 ps
CPU time 1.39 seconds
Started Jun 02 01:27:37 PM PDT 24
Finished Jun 02 01:27:39 PM PDT 24
Peak memory 197980 kb
Host smart-c4d97872-d133-4f93-9d6e-f062576c7b27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744017282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1744017282
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3778375462
Short name T817
Test name
Test status
Simulation time 95937324 ps
CPU time 1.43 seconds
Started Jun 02 01:27:41 PM PDT 24
Finished Jun 02 01:27:43 PM PDT 24
Peak memory 197920 kb
Host smart-92d30d3a-48c4-4dd2-8ed5-2b090e8e0aec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778375462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3778375462
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1633926090
Short name T83
Test name
Test status
Simulation time 24717072 ps
CPU time 0.66 seconds
Started Jun 02 01:27:18 PM PDT 24
Finished Jun 02 01:27:20 PM PDT 24
Peak memory 195252 kb
Host smart-135a8c85-c489-4a92-9093-a36edfd234d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633926090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1633926090
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2484544
Short name T75
Test name
Test status
Simulation time 388041119 ps
CPU time 3.24 seconds
Started Jun 02 01:27:18 PM PDT 24
Finished Jun 02 01:27:21 PM PDT 24
Peak memory 196632 kb
Host smart-d840577b-e57f-4aa5-8d84-88f640708a0f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2484544
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2418840238
Short name T88
Test name
Test status
Simulation time 27043827 ps
CPU time 0.63 seconds
Started Jun 02 01:27:15 PM PDT 24
Finished Jun 02 01:27:16 PM PDT 24
Peak memory 194868 kb
Host smart-d517c2e3-e1ff-4486-a291-5e8a1854a82c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418840238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2418840238
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3113807335
Short name T735
Test name
Test status
Simulation time 37481830 ps
CPU time 1.67 seconds
Started Jun 02 01:27:15 PM PDT 24
Finished Jun 02 01:27:17 PM PDT 24
Peak memory 197984 kb
Host smart-43f0c3c0-873d-44f5-8d19-b75f8111cd39
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113807335 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3113807335
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3928137298
Short name T834
Test name
Test status
Simulation time 49156961 ps
CPU time 0.58 seconds
Started Jun 02 01:27:17 PM PDT 24
Finished Jun 02 01:27:18 PM PDT 24
Peak memory 193844 kb
Host smart-3bc8bee5-7f2b-4290-a666-f3fa4d7f5296
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928137298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3928137298
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2256874677
Short name T781
Test name
Test status
Simulation time 24241719 ps
CPU time 0.59 seconds
Started Jun 02 01:27:16 PM PDT 24
Finished Jun 02 01:27:17 PM PDT 24
Peak memory 193652 kb
Host smart-e58aa087-a21f-40a0-8c7d-0b7fa02e3a86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256874677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2256874677
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4014402673
Short name T798
Test name
Test status
Simulation time 17393274 ps
CPU time 0.67 seconds
Started Jun 02 01:27:18 PM PDT 24
Finished Jun 02 01:27:19 PM PDT 24
Peak memory 194488 kb
Host smart-f109f197-edb0-4920-94c3-aa629c70c88a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014402673 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.4014402673
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1375815541
Short name T741
Test name
Test status
Simulation time 68319868 ps
CPU time 1.65 seconds
Started Jun 02 01:27:18 PM PDT 24
Finished Jun 02 01:27:20 PM PDT 24
Peak memory 197952 kb
Host smart-87d72aa8-9859-459f-8caa-9269da72696f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375815541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1375815541
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.56811463
Short name T782
Test name
Test status
Simulation time 603573928 ps
CPU time 1.16 seconds
Started Jun 02 01:27:18 PM PDT 24
Finished Jun 02 01:27:20 PM PDT 24
Peak memory 197912 kb
Host smart-db1f3d8c-1e55-45ff-9bca-9242e029ec3f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56811463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_tl_intg_err.56811463
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.8334197
Short name T755
Test name
Test status
Simulation time 37580457 ps
CPU time 0.65 seconds
Started Jun 02 01:27:37 PM PDT 24
Finished Jun 02 01:27:38 PM PDT 24
Peak memory 193616 kb
Host smart-31f66223-dd33-4c56-b08c-75eda0f79766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8334197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.8334197
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2224634127
Short name T721
Test name
Test status
Simulation time 13458647 ps
CPU time 0.62 seconds
Started Jun 02 01:27:38 PM PDT 24
Finished Jun 02 01:27:39 PM PDT 24
Peak memory 193564 kb
Host smart-de7766f0-bb66-4176-bfce-29690a9b0840
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224634127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2224634127
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3048103994
Short name T823
Test name
Test status
Simulation time 24135813 ps
CPU time 0.62 seconds
Started Jun 02 01:27:44 PM PDT 24
Finished Jun 02 01:27:45 PM PDT 24
Peak memory 193620 kb
Host smart-71e7033f-587e-4764-9db7-0514396ce19b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048103994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3048103994
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1656321510
Short name T789
Test name
Test status
Simulation time 60575380 ps
CPU time 0.61 seconds
Started Jun 02 01:27:44 PM PDT 24
Finished Jun 02 01:27:45 PM PDT 24
Peak memory 193544 kb
Host smart-f6e42259-ff29-4997-8ca6-4eb3733415d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656321510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1656321510
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.277419230
Short name T840
Test name
Test status
Simulation time 61360337 ps
CPU time 0.58 seconds
Started Jun 02 01:27:43 PM PDT 24
Finished Jun 02 01:27:44 PM PDT 24
Peak memory 193604 kb
Host smart-10fae793-9c78-44c3-813e-837993099983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277419230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.277419230
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.4185749320
Short name T813
Test name
Test status
Simulation time 20526866 ps
CPU time 0.63 seconds
Started Jun 02 01:27:42 PM PDT 24
Finished Jun 02 01:27:43 PM PDT 24
Peak memory 193656 kb
Host smart-2027804b-95ef-4d27-ae11-775cf347d579
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185749320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.4185749320
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.172658419
Short name T720
Test name
Test status
Simulation time 15481156 ps
CPU time 0.59 seconds
Started Jun 02 01:27:41 PM PDT 24
Finished Jun 02 01:27:42 PM PDT 24
Peak memory 193592 kb
Host smart-72227721-a978-4b8c-b50b-3bf2311fc03d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172658419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.172658419
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1902971262
Short name T841
Test name
Test status
Simulation time 16042886 ps
CPU time 0.62 seconds
Started Jun 02 01:27:44 PM PDT 24
Finished Jun 02 01:27:45 PM PDT 24
Peak memory 193564 kb
Host smart-18478cfd-dd09-4599-9e5d-9bae2f5e34ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902971262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1902971262
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1968087493
Short name T742
Test name
Test status
Simulation time 21147786 ps
CPU time 0.62 seconds
Started Jun 02 01:27:43 PM PDT 24
Finished Jun 02 01:27:45 PM PDT 24
Peak memory 194284 kb
Host smart-728d4891-1806-4923-8edb-4c640fed9ffb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968087493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1968087493
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.946624605
Short name T746
Test name
Test status
Simulation time 16534920 ps
CPU time 0.63 seconds
Started Jun 02 01:27:43 PM PDT 24
Finished Jun 02 01:27:44 PM PDT 24
Peak memory 193764 kb
Host smart-33e2f3b3-7358-40fb-a0fb-1b3b94805a48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946624605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.946624605
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1660570604
Short name T92
Test name
Test status
Simulation time 47912987 ps
CPU time 0.88 seconds
Started Jun 02 01:27:16 PM PDT 24
Finished Jun 02 01:27:18 PM PDT 24
Peak memory 196648 kb
Host smart-aa1981f2-10ab-4c9a-b856-d6e3f3f91221
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660570604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1660570604
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2412095782
Short name T776
Test name
Test status
Simulation time 174401910 ps
CPU time 2.44 seconds
Started Jun 02 01:27:18 PM PDT 24
Finished Jun 02 01:27:21 PM PDT 24
Peak memory 196864 kb
Host smart-3c85d4ac-2fa9-4fa0-9f5a-82cdc222c372
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412095782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2412095782
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.742116750
Short name T80
Test name
Test status
Simulation time 14796710 ps
CPU time 0.61 seconds
Started Jun 02 01:27:18 PM PDT 24
Finished Jun 02 01:27:19 PM PDT 24
Peak memory 194892 kb
Host smart-ece4541c-33b9-410d-9cab-e4ce5e1007ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742116750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.742116750
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3432711103
Short name T723
Test name
Test status
Simulation time 19930984 ps
CPU time 0.69 seconds
Started Jun 02 01:27:18 PM PDT 24
Finished Jun 02 01:27:19 PM PDT 24
Peak memory 197444 kb
Host smart-417086ad-b9c8-4609-b74c-ddcbfbb28d96
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432711103 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3432711103
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1514256195
Short name T101
Test name
Test status
Simulation time 14378253 ps
CPU time 0.61 seconds
Started Jun 02 01:27:16 PM PDT 24
Finished Jun 02 01:27:17 PM PDT 24
Peak memory 194536 kb
Host smart-716098a6-0023-4294-835c-fd2918423356
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514256195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1514256195
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2986312467
Short name T824
Test name
Test status
Simulation time 62126057 ps
CPU time 0.59 seconds
Started Jun 02 01:27:19 PM PDT 24
Finished Jun 02 01:27:20 PM PDT 24
Peak memory 193660 kb
Host smart-90609f5d-4108-4611-a1c4-351dc341f6f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986312467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2986312467
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3088565839
Short name T95
Test name
Test status
Simulation time 44745811 ps
CPU time 0.79 seconds
Started Jun 02 01:27:15 PM PDT 24
Finished Jun 02 01:27:16 PM PDT 24
Peak memory 196280 kb
Host smart-197e6a64-267d-40f6-8798-22149d77e320
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088565839 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3088565839
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1944152833
Short name T725
Test name
Test status
Simulation time 29411452 ps
CPU time 1.45 seconds
Started Jun 02 01:27:17 PM PDT 24
Finished Jun 02 01:27:19 PM PDT 24
Peak memory 197956 kb
Host smart-3f9b3619-dc5b-4df7-a94c-720ed678c07a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944152833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1944152833
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.4012806909
Short name T833
Test name
Test status
Simulation time 870582375 ps
CPU time 1.11 seconds
Started Jun 02 01:27:16 PM PDT 24
Finished Jun 02 01:27:18 PM PDT 24
Peak memory 197896 kb
Host smart-f01c701d-52ba-4988-bc49-16eb939baa34
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012806909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.4012806909
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.4226350859
Short name T804
Test name
Test status
Simulation time 39238512 ps
CPU time 0.61 seconds
Started Jun 02 01:27:43 PM PDT 24
Finished Jun 02 01:27:44 PM PDT 24
Peak memory 193592 kb
Host smart-804b7775-6e78-4331-a51c-0ccf8cc1949e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226350859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.4226350859
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1978678867
Short name T780
Test name
Test status
Simulation time 25116416 ps
CPU time 0.62 seconds
Started Jun 02 01:27:42 PM PDT 24
Finished Jun 02 01:27:43 PM PDT 24
Peak memory 193636 kb
Host smart-d610cc5d-6006-401a-a828-61d2316f5be3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978678867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1978678867
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3819245567
Short name T775
Test name
Test status
Simulation time 25326641 ps
CPU time 0.6 seconds
Started Jun 02 01:27:42 PM PDT 24
Finished Jun 02 01:27:43 PM PDT 24
Peak memory 193624 kb
Host smart-5fda4b95-d571-4ae2-838a-f8c178a19bf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819245567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3819245567
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3050238835
Short name T807
Test name
Test status
Simulation time 44036441 ps
CPU time 0.59 seconds
Started Jun 02 01:27:44 PM PDT 24
Finished Jun 02 01:27:45 PM PDT 24
Peak memory 193496 kb
Host smart-5ba92d02-cd58-4ec3-b799-ed32adf38ad6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050238835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3050238835
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3004429091
Short name T759
Test name
Test status
Simulation time 18506863 ps
CPU time 0.63 seconds
Started Jun 02 01:27:44 PM PDT 24
Finished Jun 02 01:27:45 PM PDT 24
Peak memory 193620 kb
Host smart-cb41ab7d-cb51-48ea-a2bb-92d8b23e8913
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004429091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3004429091
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1294135830
Short name T791
Test name
Test status
Simulation time 45860542 ps
CPU time 0.6 seconds
Started Jun 02 01:27:45 PM PDT 24
Finished Jun 02 01:27:46 PM PDT 24
Peak memory 193604 kb
Host smart-fd158b44-fa70-49ea-931a-256bc00b42c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294135830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1294135830
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.1559571610
Short name T757
Test name
Test status
Simulation time 15358810 ps
CPU time 0.6 seconds
Started Jun 02 01:27:43 PM PDT 24
Finished Jun 02 01:27:44 PM PDT 24
Peak memory 193572 kb
Host smart-b9ac06d4-3c36-4ef9-842c-df329a08ccc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559571610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.1559571610
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1092285590
Short name T724
Test name
Test status
Simulation time 13525857 ps
CPU time 0.62 seconds
Started Jun 02 01:27:42 PM PDT 24
Finished Jun 02 01:27:43 PM PDT 24
Peak memory 194260 kb
Host smart-4323ecfc-469d-4603-9cc7-2dabc72d5e94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092285590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1092285590
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1148861280
Short name T758
Test name
Test status
Simulation time 17499628 ps
CPU time 0.61 seconds
Started Jun 02 01:27:42 PM PDT 24
Finished Jun 02 01:27:43 PM PDT 24
Peak memory 193564 kb
Host smart-f9b6071b-3285-4f6c-a53f-0b453327cb69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148861280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1148861280
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1688727440
Short name T768
Test name
Test status
Simulation time 14300275 ps
CPU time 0.56 seconds
Started Jun 02 01:27:48 PM PDT 24
Finished Jun 02 01:27:49 PM PDT 24
Peak memory 194216 kb
Host smart-6b81812d-51c5-4c04-9c25-6484b416cf84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688727440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1688727440
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2171172960
Short name T84
Test name
Test status
Simulation time 130446322 ps
CPU time 0.84 seconds
Started Jun 02 01:27:18 PM PDT 24
Finished Jun 02 01:27:20 PM PDT 24
Peak memory 196576 kb
Host smart-2be1579a-019b-406c-9819-52a4e7d03e6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171172960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2171172960
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4106459512
Short name T784
Test name
Test status
Simulation time 3378638867 ps
CPU time 2.3 seconds
Started Jun 02 01:27:19 PM PDT 24
Finished Jun 02 01:27:22 PM PDT 24
Peak memory 197228 kb
Host smart-2bf38166-043c-4f4e-9793-26f08cabf931
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106459512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.4106459512
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3868413824
Short name T777
Test name
Test status
Simulation time 14797677 ps
CPU time 0.64 seconds
Started Jun 02 01:27:17 PM PDT 24
Finished Jun 02 01:27:18 PM PDT 24
Peak memory 194896 kb
Host smart-4d8a3d0a-864b-4714-9a06-9134f6931643
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868413824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3868413824
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.4094355130
Short name T797
Test name
Test status
Simulation time 20416210 ps
CPU time 0.69 seconds
Started Jun 02 01:27:16 PM PDT 24
Finished Jun 02 01:27:17 PM PDT 24
Peak memory 197364 kb
Host smart-1a8fdf04-5ce5-43ce-98ae-495d58c6cda5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094355130 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.4094355130
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2731815326
Short name T748
Test name
Test status
Simulation time 66789994 ps
CPU time 0.63 seconds
Started Jun 02 01:27:15 PM PDT 24
Finished Jun 02 01:27:16 PM PDT 24
Peak memory 194972 kb
Host smart-8976ad64-0330-48c8-8978-f85165448424
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731815326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2731815326
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2835761638
Short name T779
Test name
Test status
Simulation time 14910106 ps
CPU time 0.61 seconds
Started Jun 02 01:27:18 PM PDT 24
Finished Jun 02 01:27:19 PM PDT 24
Peak memory 194220 kb
Host smart-010e31d9-64bd-4b07-9e5c-b5f0665532f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835761638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2835761638
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.501587929
Short name T97
Test name
Test status
Simulation time 31328040 ps
CPU time 0.74 seconds
Started Jun 02 01:27:19 PM PDT 24
Finished Jun 02 01:27:21 PM PDT 24
Peak memory 196180 kb
Host smart-9eeea04c-5098-4b0c-b98c-3fe4d2a462ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501587929 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.501587929
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3620942350
Short name T738
Test name
Test status
Simulation time 194135866 ps
CPU time 3.76 seconds
Started Jun 02 01:27:15 PM PDT 24
Finished Jun 02 01:27:20 PM PDT 24
Peak memory 198024 kb
Host smart-d9fb279e-7837-4083-adfa-43093745d5eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620942350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3620942350
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.424366829
Short name T819
Test name
Test status
Simulation time 185266292 ps
CPU time 1.35 seconds
Started Jun 02 01:27:19 PM PDT 24
Finished Jun 02 01:27:21 PM PDT 24
Peak memory 197916 kb
Host smart-e1f3acaf-3533-4244-8a5d-23288fe906e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424366829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.424366829
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.380290278
Short name T722
Test name
Test status
Simulation time 76887335 ps
CPU time 0.6 seconds
Started Jun 02 01:27:46 PM PDT 24
Finished Jun 02 01:27:46 PM PDT 24
Peak memory 193612 kb
Host smart-ebab8eb1-5be9-40af-9455-d64adb8a8b95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380290278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.380290278
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.864034923
Short name T766
Test name
Test status
Simulation time 32191587 ps
CPU time 0.63 seconds
Started Jun 02 01:27:46 PM PDT 24
Finished Jun 02 01:27:47 PM PDT 24
Peak memory 193640 kb
Host smart-8af2ce55-f893-4f68-8600-7d478629d607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864034923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.864034923
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3221215934
Short name T747
Test name
Test status
Simulation time 16573846 ps
CPU time 0.61 seconds
Started Jun 02 01:27:43 PM PDT 24
Finished Jun 02 01:27:44 PM PDT 24
Peak memory 193628 kb
Host smart-df93e56c-6715-4446-ae45-c0302d96c31e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221215934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3221215934
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3283777872
Short name T832
Test name
Test status
Simulation time 26285058 ps
CPU time 0.59 seconds
Started Jun 02 01:27:44 PM PDT 24
Finished Jun 02 01:27:45 PM PDT 24
Peak memory 193632 kb
Host smart-8b898f98-5092-4fbb-82f7-afec54f7c1a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283777872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3283777872
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.172486525
Short name T809
Test name
Test status
Simulation time 44811997 ps
CPU time 0.6 seconds
Started Jun 02 01:27:49 PM PDT 24
Finished Jun 02 01:27:50 PM PDT 24
Peak memory 193644 kb
Host smart-eb31aef9-a3c1-47c6-9588-188957bb8d6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172486525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.172486525
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.724652793
Short name T734
Test name
Test status
Simulation time 29336224 ps
CPU time 0.62 seconds
Started Jun 02 01:27:43 PM PDT 24
Finished Jun 02 01:27:44 PM PDT 24
Peak memory 194304 kb
Host smart-38fbe8fe-5661-4358-a51e-d205a2390e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724652793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.724652793
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2919967851
Short name T772
Test name
Test status
Simulation time 13519632 ps
CPU time 0.6 seconds
Started Jun 02 01:27:48 PM PDT 24
Finished Jun 02 01:27:49 PM PDT 24
Peak memory 193580 kb
Host smart-a07267a3-bd27-4ea6-a167-a2f8084a88fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919967851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2919967851
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2972005362
Short name T743
Test name
Test status
Simulation time 44130420 ps
CPU time 0.62 seconds
Started Jun 02 01:27:42 PM PDT 24
Finished Jun 02 01:27:43 PM PDT 24
Peak memory 193664 kb
Host smart-3eaac6e9-6194-41cc-81b5-90f4eaf70549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972005362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2972005362
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.796585706
Short name T771
Test name
Test status
Simulation time 27333929 ps
CPU time 0.6 seconds
Started Jun 02 01:27:49 PM PDT 24
Finished Jun 02 01:27:50 PM PDT 24
Peak memory 194328 kb
Host smart-cd494a06-8a05-4988-8fd0-2aa1a2429862
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796585706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.796585706
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1582062482
Short name T828
Test name
Test status
Simulation time 49238761 ps
CPU time 0.59 seconds
Started Jun 02 01:27:44 PM PDT 24
Finished Jun 02 01:27:45 PM PDT 24
Peak memory 194340 kb
Host smart-2be7ef2d-b66a-476f-8daa-359d32276500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582062482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1582062482
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2123300308
Short name T740
Test name
Test status
Simulation time 18414339 ps
CPU time 0.63 seconds
Started Jun 02 01:27:25 PM PDT 24
Finished Jun 02 01:27:26 PM PDT 24
Peak memory 197276 kb
Host smart-bf96b556-71bd-4d16-abf1-d209ffce3c7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123300308 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2123300308
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2395845262
Short name T85
Test name
Test status
Simulation time 44266673 ps
CPU time 0.61 seconds
Started Jun 02 01:27:23 PM PDT 24
Finished Jun 02 01:27:24 PM PDT 24
Peak memory 194876 kb
Host smart-14fdaf26-778d-4264-b665-809a7c7ea6cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395845262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2395845262
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2538234034
Short name T744
Test name
Test status
Simulation time 14978574 ps
CPU time 0.61 seconds
Started Jun 02 01:27:24 PM PDT 24
Finished Jun 02 01:27:25 PM PDT 24
Peak memory 194308 kb
Host smart-e04807fd-0c65-4862-9229-8d9104bde3b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538234034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2538234034
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3515171904
Short name T94
Test name
Test status
Simulation time 16149713 ps
CPU time 0.7 seconds
Started Jun 02 01:27:22 PM PDT 24
Finished Jun 02 01:27:23 PM PDT 24
Peak memory 194696 kb
Host smart-e1f07461-7621-49e3-b787-04ab9c9aeac5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515171904 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3515171904
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2412339321
Short name T794
Test name
Test status
Simulation time 358298883 ps
CPU time 1.55 seconds
Started Jun 02 01:27:23 PM PDT 24
Finished Jun 02 01:27:25 PM PDT 24
Peak memory 198000 kb
Host smart-7717a66d-500d-4e56-8b1e-b45d585c5cfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412339321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2412339321
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3151854049
Short name T822
Test name
Test status
Simulation time 161178410 ps
CPU time 0.84 seconds
Started Jun 02 01:27:23 PM PDT 24
Finished Jun 02 01:27:24 PM PDT 24
Peak memory 196976 kb
Host smart-892fb072-2946-4fcd-bbb8-7def1597414d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151854049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3151854049
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1100935380
Short name T769
Test name
Test status
Simulation time 38683950 ps
CPU time 1.04 seconds
Started Jun 02 01:27:24 PM PDT 24
Finished Jun 02 01:27:26 PM PDT 24
Peak memory 197060 kb
Host smart-893a1c5a-6da8-450d-ac06-17f61dcf54ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100935380 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1100935380
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2808738200
Short name T827
Test name
Test status
Simulation time 21317829 ps
CPU time 0.61 seconds
Started Jun 02 01:27:22 PM PDT 24
Finished Jun 02 01:27:23 PM PDT 24
Peak memory 194920 kb
Host smart-8b5f4804-bdbf-40cd-b981-a967832e7cc0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808738200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2808738200
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.434967149
Short name T770
Test name
Test status
Simulation time 49007768 ps
CPU time 0.62 seconds
Started Jun 02 01:27:21 PM PDT 24
Finished Jun 02 01:27:22 PM PDT 24
Peak memory 193548 kb
Host smart-10ba819d-8235-4124-b935-474717388d47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434967149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.434967149
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1651877415
Short name T806
Test name
Test status
Simulation time 20681436 ps
CPU time 0.66 seconds
Started Jun 02 01:27:25 PM PDT 24
Finished Jun 02 01:27:26 PM PDT 24
Peak memory 194464 kb
Host smart-1592de63-6918-41ef-a884-9ca3b22c624a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651877415 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1651877415
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.910429582
Short name T737
Test name
Test status
Simulation time 444053115 ps
CPU time 3.83 seconds
Started Jun 02 01:27:21 PM PDT 24
Finished Jun 02 01:27:25 PM PDT 24
Peak memory 198264 kb
Host smart-76e49a96-0b21-45e8-b933-147aa84f0cb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910429582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.910429582
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.682307207
Short name T30
Test name
Test status
Simulation time 94018234 ps
CPU time 0.91 seconds
Started Jun 02 01:27:22 PM PDT 24
Finished Jun 02 01:27:23 PM PDT 24
Peak memory 197200 kb
Host smart-5ca1019e-beb2-4cc0-86ba-971e48764ada
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682307207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.682307207
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.610875258
Short name T763
Test name
Test status
Simulation time 37161886 ps
CPU time 0.76 seconds
Started Jun 02 01:27:22 PM PDT 24
Finished Jun 02 01:27:23 PM PDT 24
Peak memory 197856 kb
Host smart-a7658f46-d2f7-4544-9e55-7baffc74c7fd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610875258 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.610875258
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1600570075
Short name T839
Test name
Test status
Simulation time 16068332 ps
CPU time 0.64 seconds
Started Jun 02 01:27:23 PM PDT 24
Finished Jun 02 01:27:24 PM PDT 24
Peak memory 194672 kb
Host smart-ab3383c9-9f9b-4c5a-a554-95b7d045b977
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600570075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1600570075
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3230569723
Short name T731
Test name
Test status
Simulation time 58110639 ps
CPU time 0.6 seconds
Started Jun 02 01:27:26 PM PDT 24
Finished Jun 02 01:27:27 PM PDT 24
Peak memory 193540 kb
Host smart-cbffc600-b46c-4fb2-b036-89b0ef7b3782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230569723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3230569723
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1656791221
Short name T829
Test name
Test status
Simulation time 133752570 ps
CPU time 0.74 seconds
Started Jun 02 01:27:25 PM PDT 24
Finished Jun 02 01:27:27 PM PDT 24
Peak memory 196140 kb
Host smart-28b41fa9-547d-4714-8d80-1fd3fa90bfb6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656791221 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1656791221
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2933067043
Short name T792
Test name
Test status
Simulation time 128217322 ps
CPU time 1.51 seconds
Started Jun 02 01:27:23 PM PDT 24
Finished Jun 02 01:27:25 PM PDT 24
Peak memory 197940 kb
Host smart-c7cbba7d-2c88-4950-ba55-d1f0434d686e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933067043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2933067043
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3715126527
Short name T41
Test name
Test status
Simulation time 45860933 ps
CPU time 0.86 seconds
Started Jun 02 01:27:22 PM PDT 24
Finished Jun 02 01:27:23 PM PDT 24
Peak memory 196944 kb
Host smart-50750a2b-ea00-4044-845d-a8e71fc64309
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715126527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3715126527
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1806058287
Short name T793
Test name
Test status
Simulation time 141966460 ps
CPU time 0.77 seconds
Started Jun 02 01:27:23 PM PDT 24
Finished Jun 02 01:27:24 PM PDT 24
Peak memory 197804 kb
Host smart-28a94721-a1b2-4efb-9a0c-aa3557aa379c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806058287 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1806058287
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.540915095
Short name T86
Test name
Test status
Simulation time 13076538 ps
CPU time 0.6 seconds
Started Jun 02 01:27:24 PM PDT 24
Finished Jun 02 01:27:25 PM PDT 24
Peak memory 193544 kb
Host smart-4954fc95-180d-49a8-9fa0-37248afde91b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540915095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.540915095
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3917492159
Short name T732
Test name
Test status
Simulation time 84503715 ps
CPU time 0.62 seconds
Started Jun 02 01:27:24 PM PDT 24
Finished Jun 02 01:27:25 PM PDT 24
Peak memory 194292 kb
Host smart-f09567e1-dc3c-48ce-9efa-1595035cd9ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917492159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3917492159
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2406396222
Short name T82
Test name
Test status
Simulation time 45701647 ps
CPU time 0.74 seconds
Started Jun 02 01:27:23 PM PDT 24
Finished Jun 02 01:27:24 PM PDT 24
Peak memory 196840 kb
Host smart-72ad1ed8-75fe-40ab-8116-f9d23ed4b011
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406396222 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2406396222
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2445792359
Short name T739
Test name
Test status
Simulation time 320292826 ps
CPU time 2.97 seconds
Started Jun 02 01:27:22 PM PDT 24
Finished Jun 02 01:27:25 PM PDT 24
Peak memory 197968 kb
Host smart-358a80b7-d525-4201-a454-a2bf80361e50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445792359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2445792359
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3571387020
Short name T105
Test name
Test status
Simulation time 246498930 ps
CPU time 1.41 seconds
Started Jun 02 01:27:21 PM PDT 24
Finished Jun 02 01:27:23 PM PDT 24
Peak memory 198120 kb
Host smart-4d0c7761-9083-49c3-bc61-c251d7d49e0c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571387020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3571387020
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3855585450
Short name T719
Test name
Test status
Simulation time 24565562 ps
CPU time 0.77 seconds
Started Jun 02 01:27:23 PM PDT 24
Finished Jun 02 01:27:25 PM PDT 24
Peak memory 197848 kb
Host smart-3b8be645-9878-41c4-8885-3f41ff18be9e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855585450 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3855585450
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3692398951
Short name T89
Test name
Test status
Simulation time 33154986 ps
CPU time 0.61 seconds
Started Jun 02 01:27:24 PM PDT 24
Finished Jun 02 01:27:26 PM PDT 24
Peak memory 195348 kb
Host smart-202daadb-19b4-4150-bd82-8e7b47b53641
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692398951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3692398951
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.4097746714
Short name T812
Test name
Test status
Simulation time 54488668 ps
CPU time 0.61 seconds
Started Jun 02 01:27:23 PM PDT 24
Finished Jun 02 01:27:24 PM PDT 24
Peak memory 194344 kb
Host smart-b695ca55-e350-4dd1-9d4c-5de98ab54aae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097746714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.4097746714
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3523632504
Short name T814
Test name
Test status
Simulation time 35954008 ps
CPU time 0.8 seconds
Started Jun 02 01:27:22 PM PDT 24
Finished Jun 02 01:27:23 PM PDT 24
Peak memory 196600 kb
Host smart-19cafa32-4ed8-435f-89ed-3087a2abb149
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523632504 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3523632504
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.747199838
Short name T815
Test name
Test status
Simulation time 122897715 ps
CPU time 2.33 seconds
Started Jun 02 01:27:23 PM PDT 24
Finished Jun 02 01:27:26 PM PDT 24
Peak memory 197960 kb
Host smart-16031b5b-7deb-42cb-be6e-5ea417f6b3d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747199838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.747199838
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1738801964
Short name T104
Test name
Test status
Simulation time 275509687 ps
CPU time 0.9 seconds
Started Jun 02 01:27:23 PM PDT 24
Finished Jun 02 01:27:25 PM PDT 24
Peak memory 197160 kb
Host smart-6d2ed265-9f06-4fc8-83d3-0781b476807e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738801964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1738801964
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2926366226
Short name T449
Test name
Test status
Simulation time 20165138 ps
CPU time 0.55 seconds
Started Jun 02 01:42:16 PM PDT 24
Finished Jun 02 01:42:17 PM PDT 24
Peak memory 194576 kb
Host smart-66aa5ae6-b920-4122-be2d-822c3fbf44fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926366226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2926366226
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1558861407
Short name T385
Test name
Test status
Simulation time 53084440 ps
CPU time 0.87 seconds
Started Jun 02 01:42:14 PM PDT 24
Finished Jun 02 01:42:16 PM PDT 24
Peak memory 196384 kb
Host smart-d51ae2c7-dc50-4b97-b9cd-28c6ad4d9bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558861407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1558861407
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.4105100821
Short name T375
Test name
Test status
Simulation time 307603369 ps
CPU time 8.87 seconds
Started Jun 02 01:42:15 PM PDT 24
Finished Jun 02 01:42:25 PM PDT 24
Peak memory 197976 kb
Host smart-2dd9f770-bc29-4a66-8bed-1fb8c35cf45b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105100821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.4105100821
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2625848739
Short name T511
Test name
Test status
Simulation time 68833567 ps
CPU time 0.86 seconds
Started Jun 02 01:42:17 PM PDT 24
Finished Jun 02 01:42:18 PM PDT 24
Peak memory 195904 kb
Host smart-24ccebc9-aa46-4923-9c08-f737bfa58875
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625848739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2625848739
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1252156709
Short name T518
Test name
Test status
Simulation time 30923598 ps
CPU time 0.74 seconds
Started Jun 02 01:42:15 PM PDT 24
Finished Jun 02 01:42:17 PM PDT 24
Peak memory 194416 kb
Host smart-21b2f1ad-aac2-4ec9-825d-ac4ca99d6129
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252156709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1252156709
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3717873919
Short name T392
Test name
Test status
Simulation time 231867610 ps
CPU time 2.56 seconds
Started Jun 02 01:42:17 PM PDT 24
Finished Jun 02 01:42:20 PM PDT 24
Peak memory 197792 kb
Host smart-d98584a4-4fcf-46ce-a7bd-fbc75427c8f8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717873919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3717873919
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1943216749
Short name T678
Test name
Test status
Simulation time 96824563 ps
CPU time 1.04 seconds
Started Jun 02 01:42:17 PM PDT 24
Finished Jun 02 01:42:19 PM PDT 24
Peak memory 195596 kb
Host smart-902569a3-f6fd-4068-90c5-29da8f44a6d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943216749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1943216749
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2403522500
Short name T141
Test name
Test status
Simulation time 24823958 ps
CPU time 0.73 seconds
Started Jun 02 01:42:16 PM PDT 24
Finished Jun 02 01:42:18 PM PDT 24
Peak memory 195416 kb
Host smart-01f4b072-de46-47d6-817d-602781937d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403522500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2403522500
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.181690109
Short name T710
Test name
Test status
Simulation time 183789912 ps
CPU time 0.63 seconds
Started Jun 02 01:42:15 PM PDT 24
Finished Jun 02 01:42:16 PM PDT 24
Peak memory 195028 kb
Host smart-c21f7158-a3fb-4505-879a-6d9e52394d86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181690109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.181690109
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2623315656
Short name T201
Test name
Test status
Simulation time 282231132 ps
CPU time 4.04 seconds
Started Jun 02 01:42:15 PM PDT 24
Finished Jun 02 01:42:20 PM PDT 24
Peak memory 197968 kb
Host smart-0a177c1c-6593-479f-a69c-fcc4de5a9991
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623315656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2623315656
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1573591602
Short name T319
Test name
Test status
Simulation time 95525480 ps
CPU time 0.98 seconds
Started Jun 02 01:42:15 PM PDT 24
Finished Jun 02 01:42:17 PM PDT 24
Peak memory 195752 kb
Host smart-80b05345-f409-4f7c-a669-c61d4ccd4ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573591602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1573591602
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.472526960
Short name T344
Test name
Test status
Simulation time 141216875 ps
CPU time 1.12 seconds
Started Jun 02 01:42:17 PM PDT 24
Finished Jun 02 01:42:19 PM PDT 24
Peak memory 196444 kb
Host smart-c49b6d6b-067f-4153-ad40-db4af581ad9a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472526960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.472526960
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.962460270
Short name T698
Test name
Test status
Simulation time 6880903712 ps
CPU time 44.96 seconds
Started Jun 02 01:42:15 PM PDT 24
Finished Jun 02 01:43:00 PM PDT 24
Peak memory 198176 kb
Host smart-aac69cd2-0ff0-44cd-a7b8-a59f019aa7f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962460270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.962460270
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.2468277220
Short name T617
Test name
Test status
Simulation time 190152672761 ps
CPU time 1316.99 seconds
Started Jun 02 01:42:16 PM PDT 24
Finished Jun 02 02:04:13 PM PDT 24
Peak memory 198164 kb
Host smart-3e453d4f-3b41-4daa-a53d-42b90b5e18e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2468277220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.2468277220
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2021200103
Short name T211
Test name
Test status
Simulation time 96467665 ps
CPU time 0.57 seconds
Started Jun 02 01:42:22 PM PDT 24
Finished Jun 02 01:42:23 PM PDT 24
Peak memory 194576 kb
Host smart-a37d00c7-21ba-48fd-945c-bd2ec510c002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021200103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2021200103
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1880472430
Short name T687
Test name
Test status
Simulation time 61578101 ps
CPU time 0.61 seconds
Started Jun 02 01:42:15 PM PDT 24
Finished Jun 02 01:42:16 PM PDT 24
Peak memory 194012 kb
Host smart-df13a21c-a8fa-41c4-85dc-f517e06e685d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880472430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1880472430
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1093027903
Short name T600
Test name
Test status
Simulation time 167062197 ps
CPU time 9.12 seconds
Started Jun 02 01:42:15 PM PDT 24
Finished Jun 02 01:42:24 PM PDT 24
Peak memory 196844 kb
Host smart-6c6eb391-0abd-46c0-b72e-e02c00883c97
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093027903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1093027903
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3464911343
Short name T653
Test name
Test status
Simulation time 241495785 ps
CPU time 0.8 seconds
Started Jun 02 01:42:22 PM PDT 24
Finished Jun 02 01:42:23 PM PDT 24
Peak memory 195800 kb
Host smart-d4d7a483-c3e6-48de-8b9a-1546c172253e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464911343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3464911343
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3020637748
Short name T365
Test name
Test status
Simulation time 171546477 ps
CPU time 1.33 seconds
Started Jun 02 01:42:17 PM PDT 24
Finished Jun 02 01:42:19 PM PDT 24
Peak memory 197236 kb
Host smart-4b27f683-dd5a-4871-92ae-4abc62ab9a47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020637748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3020637748
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3411251108
Short name T669
Test name
Test status
Simulation time 571726062 ps
CPU time 2.48 seconds
Started Jun 02 01:42:16 PM PDT 24
Finished Jun 02 01:42:19 PM PDT 24
Peak memory 198024 kb
Host smart-7b6f7b1f-57c2-4b0b-9f27-283b6b171a60
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411251108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3411251108
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1759202155
Short name T625
Test name
Test status
Simulation time 417787234 ps
CPU time 2.99 seconds
Started Jun 02 01:42:17 PM PDT 24
Finished Jun 02 01:42:21 PM PDT 24
Peak memory 195652 kb
Host smart-50cf4a93-7d4f-4a17-953f-d27bd6a0b962
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759202155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1759202155
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1481787452
Short name T250
Test name
Test status
Simulation time 29644293 ps
CPU time 0.99 seconds
Started Jun 02 01:42:17 PM PDT 24
Finished Jun 02 01:42:18 PM PDT 24
Peak memory 196496 kb
Host smart-1a48a3ec-fd87-40e0-9b20-97719a9e4706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481787452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1481787452
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1421238448
Short name T354
Test name
Test status
Simulation time 97402834 ps
CPU time 1.08 seconds
Started Jun 02 01:42:16 PM PDT 24
Finished Jun 02 01:42:18 PM PDT 24
Peak memory 196048 kb
Host smart-bd07649c-8927-4513-831d-048ef5bad8eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421238448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1421238448
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3170386295
Short name T709
Test name
Test status
Simulation time 158687494 ps
CPU time 1.82 seconds
Started Jun 02 01:42:22 PM PDT 24
Finished Jun 02 01:42:24 PM PDT 24
Peak memory 197940 kb
Host smart-cdc92ed9-8899-4dda-a31c-747b15ed9258
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170386295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3170386295
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3953032988
Short name T44
Test name
Test status
Simulation time 74882886 ps
CPU time 0.86 seconds
Started Jun 02 01:42:22 PM PDT 24
Finished Jun 02 01:42:23 PM PDT 24
Peak memory 213908 kb
Host smart-482ed14c-841e-4368-9324-2411f5a3ccca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953032988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3953032988
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.1554381849
Short name T479
Test name
Test status
Simulation time 77454612 ps
CPU time 1.23 seconds
Started Jun 02 01:42:15 PM PDT 24
Finished Jun 02 01:42:17 PM PDT 24
Peak memory 195500 kb
Host smart-79bd3704-e38c-4fb1-9fac-6c9bb8412125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554381849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.1554381849
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3214962233
Short name T694
Test name
Test status
Simulation time 402857047 ps
CPU time 1.19 seconds
Started Jun 02 01:42:15 PM PDT 24
Finished Jun 02 01:42:17 PM PDT 24
Peak memory 195548 kb
Host smart-6ce2558d-d424-4d32-8175-85c7c5da36b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214962233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3214962233
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.519522900
Short name T276
Test name
Test status
Simulation time 4393829320 ps
CPU time 60.74 seconds
Started Jun 02 01:42:21 PM PDT 24
Finished Jun 02 01:43:22 PM PDT 24
Peak memory 198076 kb
Host smart-e44093cd-5389-4cb4-811a-09eb1fd8574a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519522900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.519522900
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3891287960
Short name T216
Test name
Test status
Simulation time 12790336 ps
CPU time 0.56 seconds
Started Jun 02 01:42:45 PM PDT 24
Finished Jun 02 01:42:46 PM PDT 24
Peak memory 194592 kb
Host smart-f13945de-bf1a-4ae4-a853-387a6ee943d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891287960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3891287960
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2021289867
Short name T305
Test name
Test status
Simulation time 33629430 ps
CPU time 0.67 seconds
Started Jun 02 01:42:38 PM PDT 24
Finished Jun 02 01:42:40 PM PDT 24
Peak memory 194184 kb
Host smart-bb39d46c-1588-4246-8559-a64cb1766eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021289867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2021289867
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1916034481
Short name T670
Test name
Test status
Simulation time 737312157 ps
CPU time 19.34 seconds
Started Jun 02 01:42:39 PM PDT 24
Finished Jun 02 01:42:59 PM PDT 24
Peak memory 196876 kb
Host smart-835e297b-3732-4c80-adb9-1a1891a501c4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916034481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1916034481
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1115527353
Short name T336
Test name
Test status
Simulation time 19481902 ps
CPU time 0.61 seconds
Started Jun 02 01:42:38 PM PDT 24
Finished Jun 02 01:42:39 PM PDT 24
Peak memory 195196 kb
Host smart-fcb23f16-92b2-480a-8705-09871c68cbe5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115527353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1115527353
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1787743982
Short name T436
Test name
Test status
Simulation time 31380716 ps
CPU time 0.75 seconds
Started Jun 02 01:42:40 PM PDT 24
Finished Jun 02 01:42:42 PM PDT 24
Peak memory 195444 kb
Host smart-756d3316-b636-4281-b089-bd60a1fee784
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787743982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1787743982
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1951607065
Short name T173
Test name
Test status
Simulation time 476689669 ps
CPU time 3.11 seconds
Started Jun 02 01:42:43 PM PDT 24
Finished Jun 02 01:42:47 PM PDT 24
Peak memory 197984 kb
Host smart-d0ea30b9-489a-4a86-962c-b5ae81aa34c6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951607065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1951607065
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3530860861
Short name T175
Test name
Test status
Simulation time 1308626404 ps
CPU time 2.4 seconds
Started Jun 02 01:42:41 PM PDT 24
Finished Jun 02 01:42:44 PM PDT 24
Peak memory 195812 kb
Host smart-947bc688-9159-49f4-97e7-8146bb13dcca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530860861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3530860861
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2389479997
Short name T620
Test name
Test status
Simulation time 29212601 ps
CPU time 1.07 seconds
Started Jun 02 01:42:43 PM PDT 24
Finished Jun 02 01:42:44 PM PDT 24
Peak memory 196256 kb
Host smart-ccf979e7-6615-492e-b592-86bf9c4e5392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389479997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2389479997
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1689000860
Short name T541
Test name
Test status
Simulation time 23833824 ps
CPU time 0.78 seconds
Started Jun 02 01:42:39 PM PDT 24
Finished Jun 02 01:42:41 PM PDT 24
Peak memory 195508 kb
Host smart-00ba8fee-8da0-474f-8a67-fc6526849c62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689000860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1689000860
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2364431472
Short name T519
Test name
Test status
Simulation time 280238282 ps
CPU time 3.43 seconds
Started Jun 02 01:42:41 PM PDT 24
Finished Jun 02 01:42:45 PM PDT 24
Peak memory 197988 kb
Host smart-31671ec4-c061-494e-8597-8a5e83ddb678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364431472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.2364431472
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.4055760060
Short name T62
Test name
Test status
Simulation time 101170552 ps
CPU time 1.39 seconds
Started Jun 02 01:42:40 PM PDT 24
Finished Jun 02 01:42:42 PM PDT 24
Peak memory 196244 kb
Host smart-fa6f0716-2e8c-4a66-bb11-ed1d37356a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055760060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.4055760060
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1449728779
Short name T605
Test name
Test status
Simulation time 104077673 ps
CPU time 1.36 seconds
Started Jun 02 01:42:40 PM PDT 24
Finished Jun 02 01:42:42 PM PDT 24
Peak memory 195520 kb
Host smart-50f0cfa2-4a42-439f-afb7-938712b5a482
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449728779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1449728779
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1478163693
Short name T416
Test name
Test status
Simulation time 45380154865 ps
CPU time 173.11 seconds
Started Jun 02 01:42:39 PM PDT 24
Finished Jun 02 01:45:33 PM PDT 24
Peak memory 198148 kb
Host smart-4e4a4a5d-c4e9-429f-ba39-76138b3406a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478163693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1478163693
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.862572374
Short name T59
Test name
Test status
Simulation time 193306372402 ps
CPU time 784.65 seconds
Started Jun 02 01:42:44 PM PDT 24
Finished Jun 02 01:55:49 PM PDT 24
Peak memory 198200 kb
Host smart-864995b6-4477-44b2-9924-ff9bbacda796
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=862572374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.862572374
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2713625495
Short name T609
Test name
Test status
Simulation time 46732086 ps
CPU time 0.57 seconds
Started Jun 02 01:42:46 PM PDT 24
Finished Jun 02 01:42:47 PM PDT 24
Peak memory 194092 kb
Host smart-1749e031-fbdb-456f-87d2-b1b41c8cd4e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713625495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2713625495
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.4170530192
Short name T279
Test name
Test status
Simulation time 33677452 ps
CPU time 0.83 seconds
Started Jun 02 01:42:47 PM PDT 24
Finished Jun 02 01:42:48 PM PDT 24
Peak memory 195988 kb
Host smart-0c672d9b-5c81-4f11-a482-773c9ff628e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170530192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.4170530192
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.3698749973
Short name T417
Test name
Test status
Simulation time 443347124 ps
CPU time 23.42 seconds
Started Jun 02 01:42:46 PM PDT 24
Finished Jun 02 01:43:10 PM PDT 24
Peak memory 197944 kb
Host smart-896c5831-e5e8-49e7-b802-c7a082049761
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698749973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3698749973
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3490611376
Short name T682
Test name
Test status
Simulation time 32450716 ps
CPU time 0.74 seconds
Started Jun 02 01:42:45 PM PDT 24
Finished Jun 02 01:42:46 PM PDT 24
Peak memory 194852 kb
Host smart-38626a59-ce53-451c-9630-3cf074b8788c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490611376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3490611376
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3766185304
Short name T393
Test name
Test status
Simulation time 184022116 ps
CPU time 1.38 seconds
Started Jun 02 01:42:45 PM PDT 24
Finished Jun 02 01:42:47 PM PDT 24
Peak memory 198012 kb
Host smart-1d14dc27-8d15-4da7-801e-eb6605c41e2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766185304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3766185304
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2458824340
Short name T424
Test name
Test status
Simulation time 1480024509 ps
CPU time 2.58 seconds
Started Jun 02 01:42:46 PM PDT 24
Finished Jun 02 01:42:49 PM PDT 24
Peak memory 197000 kb
Host smart-e8c7a471-fdcd-4fc6-95cb-f65810cb6efd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458824340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2458824340
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2695878480
Short name T415
Test name
Test status
Simulation time 84441164 ps
CPU time 0.93 seconds
Started Jun 02 01:42:45 PM PDT 24
Finished Jun 02 01:42:47 PM PDT 24
Peak memory 196676 kb
Host smart-1036718f-7658-41cf-89ca-9a1a6e464651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695878480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2695878480
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3739216551
Short name T561
Test name
Test status
Simulation time 113636313 ps
CPU time 1.32 seconds
Started Jun 02 01:42:45 PM PDT 24
Finished Jun 02 01:42:47 PM PDT 24
Peak memory 197064 kb
Host smart-530e7781-3360-4837-99e0-eceb0650b5f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739216551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3739216551
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2474160919
Short name T681
Test name
Test status
Simulation time 336220224 ps
CPU time 3.65 seconds
Started Jun 02 01:42:46 PM PDT 24
Finished Jun 02 01:42:50 PM PDT 24
Peak memory 197976 kb
Host smart-75818346-c886-4958-a0cb-b58590efc562
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474160919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2474160919
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.171355198
Short name T565
Test name
Test status
Simulation time 32174096 ps
CPU time 0.87 seconds
Started Jun 02 01:42:44 PM PDT 24
Finished Jun 02 01:42:45 PM PDT 24
Peak memory 195940 kb
Host smart-e13b103c-0428-41af-858c-483cc3719617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171355198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.171355198
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1385602624
Short name T630
Test name
Test status
Simulation time 109860360 ps
CPU time 0.82 seconds
Started Jun 02 01:42:45 PM PDT 24
Finished Jun 02 01:42:46 PM PDT 24
Peak memory 195296 kb
Host smart-c0c1c07c-5b97-4c2e-9438-2a8125985361
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385602624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1385602624
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.178616999
Short name T11
Test name
Test status
Simulation time 18738309950 ps
CPU time 70.98 seconds
Started Jun 02 01:42:48 PM PDT 24
Finished Jun 02 01:43:59 PM PDT 24
Peak memory 198112 kb
Host smart-c0383566-4de0-42e1-a51f-301943340157
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178616999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.178616999
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2986910859
Short name T439
Test name
Test status
Simulation time 19439534 ps
CPU time 0.71 seconds
Started Jun 02 01:42:47 PM PDT 24
Finished Jun 02 01:42:48 PM PDT 24
Peak memory 194072 kb
Host smart-24d770e0-c1b8-47fa-b962-8b75bf765a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986910859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2986910859
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.4244135870
Short name T202
Test name
Test status
Simulation time 471355765 ps
CPU time 15.22 seconds
Started Jun 02 01:42:54 PM PDT 24
Finished Jun 02 01:43:09 PM PDT 24
Peak memory 197936 kb
Host smart-f1017ac5-8fd2-4d2e-a458-b38d2984dc86
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244135870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.4244135870
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.4161297976
Short name T614
Test name
Test status
Simulation time 56333603 ps
CPU time 0.73 seconds
Started Jun 02 01:42:53 PM PDT 24
Finished Jun 02 01:42:54 PM PDT 24
Peak memory 194884 kb
Host smart-744f3eb8-9cd4-4205-8eb4-4438bbd67143
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161297976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.4161297976
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2706113589
Short name T127
Test name
Test status
Simulation time 178549429 ps
CPU time 0.85 seconds
Started Jun 02 01:42:46 PM PDT 24
Finished Jun 02 01:42:48 PM PDT 24
Peak memory 196752 kb
Host smart-5d5f2e62-81e8-4228-bf0f-4ede42186a3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706113589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2706113589
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.511547362
Short name T535
Test name
Test status
Simulation time 122933374 ps
CPU time 1.4 seconds
Started Jun 02 01:42:55 PM PDT 24
Finished Jun 02 01:42:56 PM PDT 24
Peak memory 196580 kb
Host smart-01e886c9-7b9c-44d0-83a6-ac0a283ba98a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511547362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.511547362
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.3162541897
Short name T463
Test name
Test status
Simulation time 1173770619 ps
CPU time 3.24 seconds
Started Jun 02 01:42:53 PM PDT 24
Finished Jun 02 01:42:57 PM PDT 24
Peak memory 198000 kb
Host smart-12365c9a-6d7c-4f08-a842-6ebf624009eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162541897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.3162541897
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.26587761
Short name T403
Test name
Test status
Simulation time 25567337 ps
CPU time 0.97 seconds
Started Jun 02 01:42:48 PM PDT 24
Finished Jun 02 01:42:49 PM PDT 24
Peak memory 195964 kb
Host smart-2625e82a-7a26-4390-b159-5837c2c5bb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26587761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.26587761
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2668222042
Short name T618
Test name
Test status
Simulation time 148662352 ps
CPU time 1.26 seconds
Started Jun 02 01:42:46 PM PDT 24
Finished Jun 02 01:42:47 PM PDT 24
Peak memory 197016 kb
Host smart-371be6f2-9820-4e90-ad0f-fea9ba379646
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668222042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2668222042
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3127393867
Short name T165
Test name
Test status
Simulation time 61856172 ps
CPU time 1.31 seconds
Started Jun 02 01:42:53 PM PDT 24
Finished Jun 02 01:42:54 PM PDT 24
Peak memory 197880 kb
Host smart-1e5f20c0-80fc-4cc4-9eaf-e874447367d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127393867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3127393867
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2833478431
Short name T131
Test name
Test status
Simulation time 150225205 ps
CPU time 1.31 seconds
Started Jun 02 01:42:44 PM PDT 24
Finished Jun 02 01:42:46 PM PDT 24
Peak memory 196720 kb
Host smart-bf693da3-99c5-41be-a9fa-10b1e9d8158c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833478431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2833478431
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.296804748
Short name T558
Test name
Test status
Simulation time 343248993 ps
CPU time 1.26 seconds
Started Jun 02 01:42:46 PM PDT 24
Finished Jun 02 01:42:48 PM PDT 24
Peak memory 196492 kb
Host smart-06966bec-5e58-4db0-9e64-2d9f2d444e29
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296804748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.296804748
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.973140315
Short name T299
Test name
Test status
Simulation time 73271753439 ps
CPU time 193.5 seconds
Started Jun 02 01:42:57 PM PDT 24
Finished Jun 02 01:46:11 PM PDT 24
Peak memory 198184 kb
Host smart-a5bc6403-305f-41de-9905-862e5716d352
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973140315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.973140315
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1029819376
Short name T704
Test name
Test status
Simulation time 207060492751 ps
CPU time 3295.07 seconds
Started Jun 02 01:42:56 PM PDT 24
Finished Jun 02 02:37:52 PM PDT 24
Peak memory 198188 kb
Host smart-5c6362ff-6565-4297-b98e-cfd2149b2831
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1029819376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1029819376
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1208714682
Short name T36
Test name
Test status
Simulation time 16094268 ps
CPU time 0.58 seconds
Started Jun 02 01:42:55 PM PDT 24
Finished Jun 02 01:42:56 PM PDT 24
Peak memory 194016 kb
Host smart-84a6bbc3-c375-45e2-8eeb-6e4fa1559495
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208714682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1208714682
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.898965422
Short name T116
Test name
Test status
Simulation time 24168662 ps
CPU time 0.82 seconds
Started Jun 02 01:42:54 PM PDT 24
Finished Jun 02 01:42:55 PM PDT 24
Peak memory 195392 kb
Host smart-0510d977-4291-45ac-96e2-5b86f7d10ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898965422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.898965422
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1222804105
Short name T232
Test name
Test status
Simulation time 585600302 ps
CPU time 19.3 seconds
Started Jun 02 01:42:53 PM PDT 24
Finished Jun 02 01:43:13 PM PDT 24
Peak memory 196620 kb
Host smart-1bb4b7d8-e1f5-4208-9ee9-5a9321564553
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222804105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1222804105
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.876176971
Short name T324
Test name
Test status
Simulation time 59112920 ps
CPU time 0.98 seconds
Started Jun 02 01:42:54 PM PDT 24
Finished Jun 02 01:42:55 PM PDT 24
Peak memory 197996 kb
Host smart-da374c5c-07a1-489a-9164-5dfee17a698a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876176971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.876176971
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2356475571
Short name T462
Test name
Test status
Simulation time 52378258 ps
CPU time 1.07 seconds
Started Jun 02 01:42:54 PM PDT 24
Finished Jun 02 01:42:55 PM PDT 24
Peak memory 196156 kb
Host smart-34ca1d9a-7132-4100-9b84-0c0a7d723e65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356475571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2356475571
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.172900556
Short name T586
Test name
Test status
Simulation time 26921141 ps
CPU time 1.17 seconds
Started Jun 02 01:42:55 PM PDT 24
Finished Jun 02 01:42:57 PM PDT 24
Peak memory 197632 kb
Host smart-43bdb9c4-f80e-4919-9596-e0ed492406f0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172900556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.172900556
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.168918025
Short name T181
Test name
Test status
Simulation time 127473690 ps
CPU time 3.66 seconds
Started Jun 02 01:42:55 PM PDT 24
Finished Jun 02 01:42:59 PM PDT 24
Peak memory 196764 kb
Host smart-0dd6b811-f5b4-4392-b992-83f498452e19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168918025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
168918025
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2017987693
Short name T361
Test name
Test status
Simulation time 22660597 ps
CPU time 0.73 seconds
Started Jun 02 01:42:55 PM PDT 24
Finished Jun 02 01:42:56 PM PDT 24
Peak memory 194368 kb
Host smart-605da6b4-99d9-4862-ae28-57fd0a0a9b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017987693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2017987693
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3210099190
Short name T235
Test name
Test status
Simulation time 25248075 ps
CPU time 1.01 seconds
Started Jun 02 01:42:56 PM PDT 24
Finished Jun 02 01:42:57 PM PDT 24
Peak memory 196532 kb
Host smart-94beda00-a4da-4b9a-912d-da9ba03377fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210099190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3210099190
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2089852730
Short name T579
Test name
Test status
Simulation time 147379443 ps
CPU time 1.53 seconds
Started Jun 02 01:42:56 PM PDT 24
Finished Jun 02 01:42:58 PM PDT 24
Peak memory 197896 kb
Host smart-dcf6307f-6f72-47fb-8691-f5e5f4e2f0b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089852730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2089852730
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1933861081
Short name T220
Test name
Test status
Simulation time 169877558 ps
CPU time 0.94 seconds
Started Jun 02 01:42:56 PM PDT 24
Finished Jun 02 01:42:57 PM PDT 24
Peak memory 195488 kb
Host smart-d27e5b35-ca51-4c60-be61-064dfe87f42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933861081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1933861081
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2706082008
Short name T15
Test name
Test status
Simulation time 36553381 ps
CPU time 1 seconds
Started Jun 02 01:42:54 PM PDT 24
Finished Jun 02 01:42:56 PM PDT 24
Peak memory 195676 kb
Host smart-11a0d490-e688-4c9d-bf34-ab300f79572d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706082008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2706082008
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.3568471399
Short name T326
Test name
Test status
Simulation time 13154219807 ps
CPU time 155.57 seconds
Started Jun 02 01:42:54 PM PDT 24
Finished Jun 02 01:45:30 PM PDT 24
Peak memory 198220 kb
Host smart-8120f68f-f2c6-4293-8614-ae25699d1b20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568471399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.3568471399
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2654147019
Short name T18
Test name
Test status
Simulation time 13005752 ps
CPU time 0.57 seconds
Started Jun 02 01:42:58 PM PDT 24
Finished Jun 02 01:42:59 PM PDT 24
Peak memory 193896 kb
Host smart-6a9fbc1b-c0fb-4373-bfbf-7cfcdd9444c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654147019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2654147019
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.4212809595
Short name T441
Test name
Test status
Simulation time 46489327 ps
CPU time 0.82 seconds
Started Jun 02 01:42:56 PM PDT 24
Finished Jun 02 01:42:57 PM PDT 24
Peak memory 196040 kb
Host smart-cfeda89e-b89e-4769-b3bd-4930cf92674c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212809595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.4212809595
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.4010891354
Short name T264
Test name
Test status
Simulation time 893522651 ps
CPU time 21.63 seconds
Started Jun 02 01:42:58 PM PDT 24
Finished Jun 02 01:43:20 PM PDT 24
Peak memory 196244 kb
Host smart-74f04b8a-e6cb-4e0d-a8a8-e4c804088cdc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010891354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.4010891354
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3815374230
Short name T610
Test name
Test status
Simulation time 90461548 ps
CPU time 0.69 seconds
Started Jun 02 01:42:57 PM PDT 24
Finished Jun 02 01:42:58 PM PDT 24
Peak memory 194808 kb
Host smart-826e76fd-66d3-4a17-b506-79b23431d473
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815374230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3815374230
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3680051487
Short name T703
Test name
Test status
Simulation time 38581730 ps
CPU time 0.71 seconds
Started Jun 02 01:42:58 PM PDT 24
Finished Jun 02 01:42:59 PM PDT 24
Peak memory 195008 kb
Host smart-cc0ae9fd-6c1f-4723-b1b2-19372fc574c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680051487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3680051487
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3946120919
Short name T52
Test name
Test status
Simulation time 49431276 ps
CPU time 2.04 seconds
Started Jun 02 01:42:58 PM PDT 24
Finished Jun 02 01:43:00 PM PDT 24
Peak memory 198012 kb
Host smart-0e144787-db2d-4171-a1f9-48eed2811343
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946120919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3946120919
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1613607951
Short name T587
Test name
Test status
Simulation time 394470257 ps
CPU time 3.15 seconds
Started Jun 02 01:42:55 PM PDT 24
Finished Jun 02 01:42:58 PM PDT 24
Peak memory 197172 kb
Host smart-6684e6b2-f999-41a6-b922-a8dee7a3c0a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613607951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1613607951
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.83043038
Short name T162
Test name
Test status
Simulation time 154865404 ps
CPU time 1.02 seconds
Started Jun 02 01:42:54 PM PDT 24
Finished Jun 02 01:42:56 PM PDT 24
Peak memory 196860 kb
Host smart-0a11ef0a-8b9a-45a6-a03b-820246da5372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83043038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.83043038
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.128407476
Short name T265
Test name
Test status
Simulation time 36678433 ps
CPU time 1.24 seconds
Started Jun 02 01:42:55 PM PDT 24
Finished Jun 02 01:42:56 PM PDT 24
Peak memory 195808 kb
Host smart-e57d0ece-d3d3-4a5a-8c28-2ed6b75c2543
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128407476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.128407476
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2230719724
Short name T482
Test name
Test status
Simulation time 187020044 ps
CPU time 4.43 seconds
Started Jun 02 01:42:55 PM PDT 24
Finished Jun 02 01:43:00 PM PDT 24
Peak memory 197904 kb
Host smart-41085bdb-6cc2-48c2-a0a6-b165cc8cf4a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230719724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2230719724
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.240646096
Short name T214
Test name
Test status
Simulation time 47448937 ps
CPU time 1.08 seconds
Started Jun 02 01:42:57 PM PDT 24
Finished Jun 02 01:42:58 PM PDT 24
Peak memory 196204 kb
Host smart-d48dea84-62a7-4693-97d4-f253e6cd7163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240646096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.240646096
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1349757128
Short name T244
Test name
Test status
Simulation time 60760235 ps
CPU time 1.36 seconds
Started Jun 02 01:42:56 PM PDT 24
Finished Jun 02 01:42:58 PM PDT 24
Peak memory 197952 kb
Host smart-f43da7f7-d8de-4f29-8a07-ed0b4291d9f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349757128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1349757128
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.316379466
Short name T315
Test name
Test status
Simulation time 86150157383 ps
CPU time 143.04 seconds
Started Jun 02 01:43:06 PM PDT 24
Finished Jun 02 01:45:30 PM PDT 24
Peak memory 198108 kb
Host smart-c0f9c84e-e944-40c9-a287-b4153c9d4aee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316379466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.316379466
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.2175613400
Short name T483
Test name
Test status
Simulation time 216681190496 ps
CPU time 1340.93 seconds
Started Jun 02 01:43:03 PM PDT 24
Finished Jun 02 02:05:24 PM PDT 24
Peak memory 198280 kb
Host smart-e9c6ce07-4508-4a5e-996d-c64b8f1a9b4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2175613400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.2175613400
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1185561389
Short name T155
Test name
Test status
Simulation time 31975275 ps
CPU time 0.57 seconds
Started Jun 02 01:43:00 PM PDT 24
Finished Jun 02 01:43:01 PM PDT 24
Peak memory 193856 kb
Host smart-3c4e8039-8320-46bc-bbc1-a0e70454958d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185561389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1185561389
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.170273716
Short name T666
Test name
Test status
Simulation time 26491023 ps
CPU time 0.79 seconds
Started Jun 02 01:43:04 PM PDT 24
Finished Jun 02 01:43:06 PM PDT 24
Peak memory 195304 kb
Host smart-66ec4b83-a0f8-43e5-b3e1-c141669635e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170273716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.170273716
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1010187488
Short name T195
Test name
Test status
Simulation time 2163395518 ps
CPU time 10.73 seconds
Started Jun 02 01:42:59 PM PDT 24
Finished Jun 02 01:43:10 PM PDT 24
Peak memory 196480 kb
Host smart-7a557409-21a4-4357-b4f3-91f315e599d6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010187488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1010187488
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3945925541
Short name T348
Test name
Test status
Simulation time 142877300 ps
CPU time 0.8 seconds
Started Jun 02 01:43:00 PM PDT 24
Finished Jun 02 01:43:01 PM PDT 24
Peak memory 195776 kb
Host smart-be71addb-b459-407d-bc08-3e4b61c9c57b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945925541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3945925541
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3368011887
Short name T288
Test name
Test status
Simulation time 38145512 ps
CPU time 0.76 seconds
Started Jun 02 01:43:00 PM PDT 24
Finished Jun 02 01:43:01 PM PDT 24
Peak memory 195496 kb
Host smart-314102be-a405-4731-a75d-5e8fa7a46522
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368011887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3368011887
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1615298907
Short name T437
Test name
Test status
Simulation time 613802265 ps
CPU time 2.75 seconds
Started Jun 02 01:43:00 PM PDT 24
Finished Jun 02 01:43:03 PM PDT 24
Peak memory 198080 kb
Host smart-19c846d8-97a3-4f60-b389-305042c72fd0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615298907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1615298907
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2432192398
Short name T568
Test name
Test status
Simulation time 102159412 ps
CPU time 2.06 seconds
Started Jun 02 01:43:02 PM PDT 24
Finished Jun 02 01:43:04 PM PDT 24
Peak memory 196012 kb
Host smart-b31f5165-dfa1-4fc6-af7d-0a6b3b5192b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432192398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2432192398
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.4112968451
Short name T528
Test name
Test status
Simulation time 79338726 ps
CPU time 1.05 seconds
Started Jun 02 01:43:01 PM PDT 24
Finished Jun 02 01:43:03 PM PDT 24
Peak memory 196608 kb
Host smart-dcd689e7-b458-4c70-b52f-228e1ec1a978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112968451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.4112968451
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2787781178
Short name T418
Test name
Test status
Simulation time 65811158 ps
CPU time 1.34 seconds
Started Jun 02 01:43:00 PM PDT 24
Finished Jun 02 01:43:02 PM PDT 24
Peak memory 197052 kb
Host smart-92a2ddf0-b0a6-4b19-b4fe-97c71bddd2f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787781178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2787781178
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1715889012
Short name T6
Test name
Test status
Simulation time 95689709 ps
CPU time 1.54 seconds
Started Jun 02 01:43:02 PM PDT 24
Finished Jun 02 01:43:04 PM PDT 24
Peak memory 197904 kb
Host smart-02c565c4-1d95-4a94-8f88-b224ab902cc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715889012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1715889012
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2118530543
Short name T654
Test name
Test status
Simulation time 139830603 ps
CPU time 0.87 seconds
Started Jun 02 01:42:59 PM PDT 24
Finished Jun 02 01:43:01 PM PDT 24
Peak memory 195288 kb
Host smart-4467a2be-095e-4d3f-9ad8-9096063bae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118530543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2118530543
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2930462362
Short name T267
Test name
Test status
Simulation time 62674114 ps
CPU time 1.06 seconds
Started Jun 02 01:43:05 PM PDT 24
Finished Jun 02 01:43:06 PM PDT 24
Peak memory 196160 kb
Host smart-ec963e3c-6bd7-4eb9-adaa-b0ad03648583
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930462362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2930462362
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2759676098
Short name T256
Test name
Test status
Simulation time 80357277693 ps
CPU time 203.42 seconds
Started Jun 02 01:43:03 PM PDT 24
Finished Jun 02 01:46:27 PM PDT 24
Peak memory 198164 kb
Host smart-913435d3-8243-40f5-8fe9-b8a4baf4038b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759676098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2759676098
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1369543399
Short name T197
Test name
Test status
Simulation time 29909656 ps
CPU time 0.56 seconds
Started Jun 02 01:42:59 PM PDT 24
Finished Jun 02 01:43:00 PM PDT 24
Peak memory 194544 kb
Host smart-5ca586b1-fdcc-4cf6-a187-29105a02b206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369543399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1369543399
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3833692229
Short name T583
Test name
Test status
Simulation time 42455420 ps
CPU time 0.92 seconds
Started Jun 02 01:43:01 PM PDT 24
Finished Jun 02 01:43:03 PM PDT 24
Peak memory 196564 kb
Host smart-11838ffc-ae25-423d-addf-602a795cfe11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833692229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3833692229
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2275823945
Short name T550
Test name
Test status
Simulation time 401923048 ps
CPU time 13.4 seconds
Started Jun 02 01:42:59 PM PDT 24
Finished Jun 02 01:43:12 PM PDT 24
Peak memory 197972 kb
Host smart-1cd8dd45-3163-4ef6-b9e7-eb554127c921
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275823945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2275823945
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2316286018
Short name T368
Test name
Test status
Simulation time 64716371 ps
CPU time 0.88 seconds
Started Jun 02 01:43:04 PM PDT 24
Finished Jun 02 01:43:06 PM PDT 24
Peak memory 196780 kb
Host smart-5ef35123-b343-45f9-bf27-dbee830ef1ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316286018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2316286018
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1549320638
Short name T677
Test name
Test status
Simulation time 41220912 ps
CPU time 1.2 seconds
Started Jun 02 01:43:01 PM PDT 24
Finished Jun 02 01:43:03 PM PDT 24
Peak memory 195816 kb
Host smart-59b78b10-9b1d-4984-86b7-8bd65245066a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549320638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1549320638
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1821477737
Short name T492
Test name
Test status
Simulation time 268532797 ps
CPU time 3 seconds
Started Jun 02 01:43:21 PM PDT 24
Finished Jun 02 01:43:25 PM PDT 24
Peak memory 197952 kb
Host smart-9f958956-6f4f-496d-bed0-53e8a1bdd7f6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821477737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1821477737
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.4273791837
Short name T188
Test name
Test status
Simulation time 38693492 ps
CPU time 1.03 seconds
Started Jun 02 01:43:01 PM PDT 24
Finished Jun 02 01:43:02 PM PDT 24
Peak memory 195752 kb
Host smart-9589cd49-9c81-4a12-9b01-fca5a1ffcf6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273791837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.4273791837
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1275038132
Short name T158
Test name
Test status
Simulation time 25165409 ps
CPU time 1.05 seconds
Started Jun 02 01:43:02 PM PDT 24
Finished Jun 02 01:43:04 PM PDT 24
Peak memory 195788 kb
Host smart-eb480196-7b55-4141-954a-ae6b34bfc0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275038132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1275038132
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2677585689
Short name T148
Test name
Test status
Simulation time 143755949 ps
CPU time 0.97 seconds
Started Jun 02 01:43:01 PM PDT 24
Finished Jun 02 01:43:02 PM PDT 24
Peak memory 196012 kb
Host smart-4b3295e4-a67a-41d1-a053-e1f9a25621b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677585689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2677585689
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3196230738
Short name T453
Test name
Test status
Simulation time 1643324359 ps
CPU time 4.99 seconds
Started Jun 02 01:43:06 PM PDT 24
Finished Jun 02 01:43:12 PM PDT 24
Peak memory 197920 kb
Host smart-e1cedea2-5bec-44fa-afe8-137b6d424a15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196230738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3196230738
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.726815202
Short name T125
Test name
Test status
Simulation time 135024024 ps
CPU time 0.95 seconds
Started Jun 02 01:42:59 PM PDT 24
Finished Jun 02 01:43:00 PM PDT 24
Peak memory 195760 kb
Host smart-d978df23-efc1-498e-9cd9-2d9227bc67a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726815202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.726815202
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.498700245
Short name T198
Test name
Test status
Simulation time 35687263 ps
CPU time 1.03 seconds
Started Jun 02 01:43:00 PM PDT 24
Finished Jun 02 01:43:01 PM PDT 24
Peak memory 195492 kb
Host smart-e0e77fa1-e050-4112-b5aa-a9e260798ab4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498700245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.498700245
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.4007214957
Short name T646
Test name
Test status
Simulation time 33876332073 ps
CPU time 187.06 seconds
Started Jun 02 01:43:01 PM PDT 24
Finished Jun 02 01:46:08 PM PDT 24
Peak memory 198156 kb
Host smart-88da32b4-1f04-4b60-9c04-d9b8db010ecf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007214957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.4007214957
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1234219384
Short name T635
Test name
Test status
Simulation time 57802133 ps
CPU time 0.57 seconds
Started Jun 02 01:43:07 PM PDT 24
Finished Jun 02 01:43:08 PM PDT 24
Peak memory 194584 kb
Host smart-34e41dec-0918-414a-8b5c-d42d58783603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234219384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1234219384
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3787526398
Short name T171
Test name
Test status
Simulation time 146473246 ps
CPU time 0.85 seconds
Started Jun 02 01:43:04 PM PDT 24
Finished Jun 02 01:43:05 PM PDT 24
Peak memory 195292 kb
Host smart-2f0373a6-4e59-48a3-a983-3941be9aa618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787526398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3787526398
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2160507796
Short name T649
Test name
Test status
Simulation time 2616854494 ps
CPU time 25.7 seconds
Started Jun 02 01:43:01 PM PDT 24
Finished Jun 02 01:43:27 PM PDT 24
Peak memory 196868 kb
Host smart-16762848-bdea-44b7-9299-817fa7e75240
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160507796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2160507796
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.237096496
Short name T426
Test name
Test status
Simulation time 265066151 ps
CPU time 0.96 seconds
Started Jun 02 01:43:03 PM PDT 24
Finished Jun 02 01:43:05 PM PDT 24
Peak memory 196136 kb
Host smart-60b91021-5315-444c-9682-4866ff348d39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237096496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.237096496
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3452170998
Short name T536
Test name
Test status
Simulation time 321929157 ps
CPU time 1.46 seconds
Started Jun 02 01:42:59 PM PDT 24
Finished Jun 02 01:43:01 PM PDT 24
Peak memory 197168 kb
Host smart-97d4ada8-bba3-470c-9f38-b52eca7ab66d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452170998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3452170998
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3772317685
Short name T108
Test name
Test status
Simulation time 251696317 ps
CPU time 2.51 seconds
Started Jun 02 01:43:04 PM PDT 24
Finished Jun 02 01:43:07 PM PDT 24
Peak memory 198028 kb
Host smart-d8d13c3c-be32-416e-a804-a1e4feeaa989
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772317685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3772317685
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3991241582
Short name T182
Test name
Test status
Simulation time 51968959 ps
CPU time 1.64 seconds
Started Jun 02 01:43:02 PM PDT 24
Finished Jun 02 01:43:04 PM PDT 24
Peak memory 196468 kb
Host smart-1f379366-e1f6-45a0-a663-6b88b29d86c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991241582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3991241582
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1815568181
Short name T619
Test name
Test status
Simulation time 27518151 ps
CPU time 1.07 seconds
Started Jun 02 01:43:01 PM PDT 24
Finished Jun 02 01:43:03 PM PDT 24
Peak memory 196024 kb
Host smart-c7aa3edd-c702-4f35-84b5-88c5a3a23522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815568181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1815568181
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3891205991
Short name T475
Test name
Test status
Simulation time 57578553 ps
CPU time 1.22 seconds
Started Jun 02 01:43:00 PM PDT 24
Finished Jun 02 01:43:02 PM PDT 24
Peak memory 197160 kb
Host smart-8f327bc8-3c4a-4058-b071-8119f495448f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891205991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3891205991
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1415696764
Short name T690
Test name
Test status
Simulation time 685051692 ps
CPU time 5.85 seconds
Started Jun 02 01:43:02 PM PDT 24
Finished Jun 02 01:43:08 PM PDT 24
Peak memory 197928 kb
Host smart-9f027085-69d9-4373-b0e0-e0436891125d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415696764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1415696764
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3523688879
Short name T271
Test name
Test status
Simulation time 80073304 ps
CPU time 0.96 seconds
Started Jun 02 01:43:00 PM PDT 24
Finished Jun 02 01:43:02 PM PDT 24
Peak memory 197104 kb
Host smart-4ecda114-6bf2-48f4-8e97-04c163f75e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523688879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3523688879
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.86491898
Short name T199
Test name
Test status
Simulation time 123083950 ps
CPU time 0.9 seconds
Started Jun 02 01:43:01 PM PDT 24
Finished Jun 02 01:43:02 PM PDT 24
Peak memory 196500 kb
Host smart-a28929f2-2b63-46d2-b1b0-94eac57f733c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86491898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.86491898
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.4019310653
Short name T623
Test name
Test status
Simulation time 5230833852 ps
CPU time 35.98 seconds
Started Jun 02 01:43:05 PM PDT 24
Finished Jun 02 01:43:42 PM PDT 24
Peak memory 198312 kb
Host smart-0bbab77b-05e8-4f49-9d66-08593e055d2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019310653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.4019310653
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1606396658
Short name T671
Test name
Test status
Simulation time 32206416 ps
CPU time 0.62 seconds
Started Jun 02 01:43:08 PM PDT 24
Finished Jun 02 01:43:09 PM PDT 24
Peak memory 194580 kb
Host smart-92477457-905d-44cd-b114-98543fcbaf42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606396658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1606396658
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3380609254
Short name T650
Test name
Test status
Simulation time 30009384 ps
CPU time 0.63 seconds
Started Jun 02 01:43:08 PM PDT 24
Finished Jun 02 01:43:09 PM PDT 24
Peak memory 194012 kb
Host smart-0a0ab0b2-7dcd-47e1-af1a-62a08e5dddbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380609254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3380609254
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1221663811
Short name T200
Test name
Test status
Simulation time 202760885 ps
CPU time 10.59 seconds
Started Jun 02 01:43:08 PM PDT 24
Finished Jun 02 01:43:19 PM PDT 24
Peak memory 195448 kb
Host smart-0d3da5fa-2570-427c-ab99-2e8d6f441225
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221663811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1221663811
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2358033499
Short name T61
Test name
Test status
Simulation time 24557385 ps
CPU time 0.62 seconds
Started Jun 02 01:43:05 PM PDT 24
Finished Jun 02 01:43:06 PM PDT 24
Peak memory 194524 kb
Host smart-fbf73404-bed7-4443-92ce-7b59e0295956
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358033499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2358033499
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.522152045
Short name T592
Test name
Test status
Simulation time 62344206 ps
CPU time 1.14 seconds
Started Jun 02 01:43:11 PM PDT 24
Finished Jun 02 01:43:12 PM PDT 24
Peak memory 195724 kb
Host smart-855f90c7-ee49-454d-a72c-94cedc557fd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522152045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.522152045
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1965576894
Short name T542
Test name
Test status
Simulation time 305299498 ps
CPU time 3.01 seconds
Started Jun 02 01:43:08 PM PDT 24
Finished Jun 02 01:43:11 PM PDT 24
Peak memory 197888 kb
Host smart-3058d96e-761b-4761-ad4e-029d9acca967
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965576894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1965576894
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1347553859
Short name T151
Test name
Test status
Simulation time 279008372 ps
CPU time 3.27 seconds
Started Jun 02 01:43:07 PM PDT 24
Finished Jun 02 01:43:10 PM PDT 24
Peak memory 197060 kb
Host smart-87303b9f-1136-45ec-ac4e-f9f386460e2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347553859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1347553859
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2348523345
Short name T572
Test name
Test status
Simulation time 24748999 ps
CPU time 0.91 seconds
Started Jun 02 01:43:07 PM PDT 24
Finished Jun 02 01:43:08 PM PDT 24
Peak memory 195852 kb
Host smart-fb6069a2-4c79-4b5f-87bb-01da60c20515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348523345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2348523345
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.4202972722
Short name T591
Test name
Test status
Simulation time 56498777 ps
CPU time 1.1 seconds
Started Jun 02 01:43:08 PM PDT 24
Finished Jun 02 01:43:10 PM PDT 24
Peak memory 195932 kb
Host smart-adc78093-f2f5-41cc-a42b-f6da25154f4c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202972722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.4202972722
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1638400452
Short name T363
Test name
Test status
Simulation time 113183238 ps
CPU time 1.4 seconds
Started Jun 02 01:43:10 PM PDT 24
Finished Jun 02 01:43:12 PM PDT 24
Peak memory 197944 kb
Host smart-4020fb61-e000-44d2-8c06-155b7ff2d070
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638400452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1638400452
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2539867519
Short name T112
Test name
Test status
Simulation time 314457651 ps
CPU time 1.57 seconds
Started Jun 02 01:43:07 PM PDT 24
Finished Jun 02 01:43:09 PM PDT 24
Peak memory 196816 kb
Host smart-5b4f7f92-0a94-4d26-af1a-8dc0f0daff24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539867519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2539867519
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2660313781
Short name T133
Test name
Test status
Simulation time 104785614 ps
CPU time 0.94 seconds
Started Jun 02 01:43:10 PM PDT 24
Finished Jun 02 01:43:12 PM PDT 24
Peak memory 195792 kb
Host smart-7804f1d1-d6a3-4f79-90e2-8f6491108694
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660313781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2660313781
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_alert_test.172806173
Short name T283
Test name
Test status
Simulation time 12464937 ps
CPU time 0.57 seconds
Started Jun 02 01:43:07 PM PDT 24
Finished Jun 02 01:43:08 PM PDT 24
Peak memory 193884 kb
Host smart-1e47867b-1e21-46b6-b247-46d3bcd9d48f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172806173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.172806173
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2179049679
Short name T143
Test name
Test status
Simulation time 64746125 ps
CPU time 0.63 seconds
Started Jun 02 01:43:07 PM PDT 24
Finished Jun 02 01:43:08 PM PDT 24
Peak memory 194776 kb
Host smart-6f7fda46-967b-48ac-a0d7-98c2240bc0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179049679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2179049679
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3355486326
Short name T651
Test name
Test status
Simulation time 527457754 ps
CPU time 7.34 seconds
Started Jun 02 01:43:07 PM PDT 24
Finished Jun 02 01:43:15 PM PDT 24
Peak memory 197080 kb
Host smart-45a96f34-196d-4241-bbcc-3fb9c9edb996
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355486326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3355486326
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1078757186
Short name T602
Test name
Test status
Simulation time 48222185 ps
CPU time 0.91 seconds
Started Jun 02 01:43:07 PM PDT 24
Finished Jun 02 01:43:09 PM PDT 24
Peak memory 197180 kb
Host smart-27928a51-e484-4031-be9c-a3b298187820
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078757186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1078757186
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.4182827906
Short name T438
Test name
Test status
Simulation time 924515064 ps
CPU time 1.34 seconds
Started Jun 02 01:43:06 PM PDT 24
Finished Jun 02 01:43:08 PM PDT 24
Peak memory 195888 kb
Host smart-bb37785d-ec17-44d4-9f53-644582785e8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182827906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.4182827906
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1643816063
Short name T444
Test name
Test status
Simulation time 91295834 ps
CPU time 3.76 seconds
Started Jun 02 01:43:09 PM PDT 24
Finished Jun 02 01:43:14 PM PDT 24
Peak memory 197968 kb
Host smart-4f63accd-dc9f-4d66-9183-f8e98ab70e0f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643816063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1643816063
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3599665956
Short name T317
Test name
Test status
Simulation time 148718863 ps
CPU time 2.93 seconds
Started Jun 02 01:43:07 PM PDT 24
Finished Jun 02 01:43:11 PM PDT 24
Peak memory 195832 kb
Host smart-0d36be60-2a7b-4e48-af6d-ebd85b3391ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599665956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3599665956
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.2131049823
Short name T293
Test name
Test status
Simulation time 37123760 ps
CPU time 1.01 seconds
Started Jun 02 01:43:08 PM PDT 24
Finished Jun 02 01:43:09 PM PDT 24
Peak memory 195844 kb
Host smart-8085d498-a37d-44e5-95f2-b2890095bfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131049823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2131049823
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1307765323
Short name T312
Test name
Test status
Simulation time 69519174 ps
CPU time 0.71 seconds
Started Jun 02 01:43:08 PM PDT 24
Finished Jun 02 01:43:09 PM PDT 24
Peak memory 195300 kb
Host smart-853aa882-55f0-4e31-8caa-ecd1aa51e532
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307765323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1307765323
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.17848927
Short name T699
Test name
Test status
Simulation time 328084436 ps
CPU time 1.5 seconds
Started Jun 02 01:43:06 PM PDT 24
Finished Jun 02 01:43:07 PM PDT 24
Peak memory 197952 kb
Host smart-73e0db4a-55ae-43ad-9aca-39c61e166277
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17848927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand
om_long_reg_writes_reg_reads.17848927
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2699739196
Short name T421
Test name
Test status
Simulation time 85406206 ps
CPU time 0.95 seconds
Started Jun 02 01:43:08 PM PDT 24
Finished Jun 02 01:43:09 PM PDT 24
Peak memory 196308 kb
Host smart-0c50273d-91f7-4060-be28-388ae21a5730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699739196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2699739196
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1344689290
Short name T435
Test name
Test status
Simulation time 65089550 ps
CPU time 1.27 seconds
Started Jun 02 01:43:08 PM PDT 24
Finished Jun 02 01:43:10 PM PDT 24
Peak memory 195876 kb
Host smart-195f86a8-e062-41c1-9659-57db3a652953
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344689290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1344689290
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.227822019
Short name T203
Test name
Test status
Simulation time 59846654255 ps
CPU time 43.89 seconds
Started Jun 02 01:43:07 PM PDT 24
Finished Jun 02 01:43:51 PM PDT 24
Peak memory 198104 kb
Host smart-114fd878-a0c9-44c0-9b1c-adf93054ced3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227822019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.227822019
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.33122366
Short name T540
Test name
Test status
Simulation time 165859177683 ps
CPU time 2090.76 seconds
Started Jun 02 01:43:07 PM PDT 24
Finished Jun 02 02:17:58 PM PDT 24
Peak memory 198216 kb
Host smart-872f262a-6d85-4e81-aea0-31ac993be75e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=33122366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.33122366
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2419176271
Short name T404
Test name
Test status
Simulation time 35649454 ps
CPU time 0.57 seconds
Started Jun 02 01:42:20 PM PDT 24
Finished Jun 02 01:42:21 PM PDT 24
Peak memory 193860 kb
Host smart-691e732d-01cd-4929-8c0a-a60947da1cee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419176271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2419176271
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3292335546
Short name T532
Test name
Test status
Simulation time 139621946 ps
CPU time 0.8 seconds
Started Jun 02 01:42:21 PM PDT 24
Finished Jun 02 01:42:23 PM PDT 24
Peak memory 195272 kb
Host smart-b6ebfb0d-fc04-454f-8dce-92310711e4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292335546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3292335546
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3219447968
Short name T476
Test name
Test status
Simulation time 3206147018 ps
CPU time 28.11 seconds
Started Jun 02 01:42:22 PM PDT 24
Finished Jun 02 01:42:51 PM PDT 24
Peak memory 196712 kb
Host smart-ff8b98e9-9ee2-4af0-92cf-8211458e3b90
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219447968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3219447968
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1028971454
Short name T632
Test name
Test status
Simulation time 27792275 ps
CPU time 0.74 seconds
Started Jun 02 01:42:20 PM PDT 24
Finished Jun 02 01:42:21 PM PDT 24
Peak memory 194828 kb
Host smart-d9f8cf1d-7e8c-4d66-a46e-e7c55e6453dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028971454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1028971454
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3127642189
Short name T557
Test name
Test status
Simulation time 95909469 ps
CPU time 1.28 seconds
Started Jun 02 01:42:21 PM PDT 24
Finished Jun 02 01:42:23 PM PDT 24
Peak memory 197064 kb
Host smart-7805b6f0-9dc6-47ee-ae5c-1e50af86d6b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127642189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3127642189
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.247673746
Short name T262
Test name
Test status
Simulation time 230639836 ps
CPU time 2.62 seconds
Started Jun 02 01:42:23 PM PDT 24
Finished Jun 02 01:42:26 PM PDT 24
Peak memory 197980 kb
Host smart-6b1b8bff-83a3-4719-a955-fa299f113f35
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247673746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.247673746
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2366203776
Short name T157
Test name
Test status
Simulation time 106318094 ps
CPU time 2.98 seconds
Started Jun 02 01:42:20 PM PDT 24
Finished Jun 02 01:42:24 PM PDT 24
Peak memory 197068 kb
Host smart-f32dbafa-7f07-4abe-b9ab-d8784a0534c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366203776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2366203776
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.4118357928
Short name T229
Test name
Test status
Simulation time 75226883 ps
CPU time 1.31 seconds
Started Jun 02 01:42:25 PM PDT 24
Finished Jun 02 01:42:26 PM PDT 24
Peak memory 196972 kb
Host smart-fe07d002-65ae-4f09-a5b8-653e85b24e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118357928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.4118357928
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.749669408
Short name T49
Test name
Test status
Simulation time 132593406 ps
CPU time 1.07 seconds
Started Jun 02 01:42:21 PM PDT 24
Finished Jun 02 01:42:23 PM PDT 24
Peak memory 195984 kb
Host smart-0d6fa42a-480f-44c0-967c-a3ace013cf6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749669408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.749669408
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1396193602
Short name T491
Test name
Test status
Simulation time 42803693 ps
CPU time 1.91 seconds
Started Jun 02 01:42:23 PM PDT 24
Finished Jun 02 01:42:25 PM PDT 24
Peak memory 197844 kb
Host smart-187b5291-c562-4d6e-9936-5e9cc863de8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396193602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1396193602
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.51601564
Short name T33
Test name
Test status
Simulation time 150238753 ps
CPU time 0.92 seconds
Started Jun 02 01:42:21 PM PDT 24
Finished Jun 02 01:42:23 PM PDT 24
Peak memory 214028 kb
Host smart-40c14b37-c195-4257-846d-f026a3f32f60
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51601564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.51601564
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3216573298
Short name T122
Test name
Test status
Simulation time 99326966 ps
CPU time 0.84 seconds
Started Jun 02 01:42:20 PM PDT 24
Finished Jun 02 01:42:22 PM PDT 24
Peak memory 195376 kb
Host smart-13bf460e-2dcd-45b4-8808-25847a60fb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216573298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3216573298
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2115363414
Short name T510
Test name
Test status
Simulation time 59161304 ps
CPU time 1.19 seconds
Started Jun 02 01:42:20 PM PDT 24
Finished Jun 02 01:42:22 PM PDT 24
Peak memory 195692 kb
Host smart-8239d282-097a-410d-9968-0c2b05251848
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115363414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2115363414
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2591801780
Short name T672
Test name
Test status
Simulation time 17018571839 ps
CPU time 183.4 seconds
Started Jun 02 01:42:23 PM PDT 24
Finished Jun 02 01:45:27 PM PDT 24
Peak memory 198112 kb
Host smart-4f19c4a3-2af4-4211-8799-d6b6d5d88970
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591801780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2591801780
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.528312451
Short name T402
Test name
Test status
Simulation time 40478205 ps
CPU time 0.55 seconds
Started Jun 02 01:43:10 PM PDT 24
Finished Jun 02 01:43:11 PM PDT 24
Peak memory 194548 kb
Host smart-4ca02fff-8cf5-4b5f-b4fa-16fdb75662aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528312451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.528312451
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.4046166965
Short name T156
Test name
Test status
Simulation time 48373180 ps
CPU time 0.77 seconds
Started Jun 02 01:43:12 PM PDT 24
Finished Jun 02 01:43:14 PM PDT 24
Peak memory 195132 kb
Host smart-c1ecf420-0c95-41c9-9ed3-0ffde81da54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046166965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.4046166965
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.456124168
Short name T396
Test name
Test status
Simulation time 120802626 ps
CPU time 5.75 seconds
Started Jun 02 01:43:18 PM PDT 24
Finished Jun 02 01:43:24 PM PDT 24
Peak memory 196256 kb
Host smart-c9959da2-999f-430d-9ef3-075a9cf58259
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456124168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.456124168
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2226282580
Short name T599
Test name
Test status
Simulation time 236475111 ps
CPU time 0.95 seconds
Started Jun 02 01:43:15 PM PDT 24
Finished Jun 02 01:43:16 PM PDT 24
Peak memory 196796 kb
Host smart-a21885c0-711f-459a-93bb-7a68711aab1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226282580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2226282580
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.3280337370
Short name T160
Test name
Test status
Simulation time 80059888 ps
CPU time 1.17 seconds
Started Jun 02 01:43:16 PM PDT 24
Finished Jun 02 01:43:18 PM PDT 24
Peak memory 196000 kb
Host smart-e8512303-0f15-4d3f-a2b3-6ea040a24212
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280337370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.3280337370
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2598384603
Short name T448
Test name
Test status
Simulation time 46753702 ps
CPU time 2.02 seconds
Started Jun 02 01:43:17 PM PDT 24
Finished Jun 02 01:43:19 PM PDT 24
Peak memory 198004 kb
Host smart-07d6d7ec-60dd-4637-a8d3-466cd205a5f7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598384603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2598384603
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.4044128935
Short name T146
Test name
Test status
Simulation time 573999623 ps
CPU time 3.18 seconds
Started Jun 02 01:43:12 PM PDT 24
Finished Jun 02 01:43:16 PM PDT 24
Peak memory 197004 kb
Host smart-f836bf7f-17c7-4256-a64b-38605647f132
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044128935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.4044128935
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.583876357
Short name T153
Test name
Test status
Simulation time 66221598 ps
CPU time 0.95 seconds
Started Jun 02 01:43:07 PM PDT 24
Finished Jun 02 01:43:09 PM PDT 24
Peak memory 195988 kb
Host smart-24b186c1-9a2f-4c7b-b1fb-c8ba7d7fa7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583876357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.583876357
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2633710343
Short name T517
Test name
Test status
Simulation time 70034469 ps
CPU time 0.71 seconds
Started Jun 02 01:43:06 PM PDT 24
Finished Jun 02 01:43:07 PM PDT 24
Peak memory 195476 kb
Host smart-8d26853c-9037-4309-a002-b3849338d1f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633710343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2633710343
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1340183328
Short name T70
Test name
Test status
Simulation time 805911826 ps
CPU time 4.85 seconds
Started Jun 02 01:43:12 PM PDT 24
Finished Jun 02 01:43:17 PM PDT 24
Peak memory 197940 kb
Host smart-9ccac472-f3de-4b69-b954-f7069afb9299
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340183328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1340183328
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3925970929
Short name T642
Test name
Test status
Simulation time 94233848 ps
CPU time 1.39 seconds
Started Jun 02 01:43:05 PM PDT 24
Finished Jun 02 01:43:07 PM PDT 24
Peak memory 196744 kb
Host smart-8a7737d1-2c07-4434-894d-4e93828623a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925970929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3925970929
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3895513312
Short name T207
Test name
Test status
Simulation time 65377794 ps
CPU time 1.37 seconds
Started Jun 02 01:43:09 PM PDT 24
Finished Jun 02 01:43:11 PM PDT 24
Peak memory 198028 kb
Host smart-21d01744-5d91-4b45-bd5f-fbb03a628308
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895513312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3895513312
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3919687133
Short name T601
Test name
Test status
Simulation time 54154656992 ps
CPU time 220.45 seconds
Started Jun 02 01:43:17 PM PDT 24
Finished Jun 02 01:46:58 PM PDT 24
Peak memory 198128 kb
Host smart-3261cef4-4d9c-4b67-b08d-11e691220526
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919687133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3919687133
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.921984209
Short name T576
Test name
Test status
Simulation time 40441859182 ps
CPU time 562.98 seconds
Started Jun 02 01:43:15 PM PDT 24
Finished Jun 02 01:52:39 PM PDT 24
Peak memory 198164 kb
Host smart-48e5f604-fcda-485c-97ed-ff9255f4e7af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=921984209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.921984209
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1326685464
Short name T170
Test name
Test status
Simulation time 32944797 ps
CPU time 0.61 seconds
Started Jun 02 01:43:16 PM PDT 24
Finished Jun 02 01:43:17 PM PDT 24
Peak memory 194560 kb
Host smart-478342d6-89c2-41a7-be10-41101097855a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326685464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1326685464
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3921678172
Short name T228
Test name
Test status
Simulation time 72023993 ps
CPU time 0.92 seconds
Started Jun 02 01:43:13 PM PDT 24
Finished Jun 02 01:43:14 PM PDT 24
Peak memory 196768 kb
Host smart-3ae73cc6-42b8-4a8b-93cc-2545d49d1dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921678172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3921678172
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2637511343
Short name T311
Test name
Test status
Simulation time 1593406984 ps
CPU time 25.79 seconds
Started Jun 02 01:43:17 PM PDT 24
Finished Jun 02 01:43:43 PM PDT 24
Peak memory 197964 kb
Host smart-db7dc438-b935-495f-87cb-40075a5d357f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637511343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2637511343
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2202658866
Short name T712
Test name
Test status
Simulation time 34172288 ps
CPU time 0.73 seconds
Started Jun 02 01:43:14 PM PDT 24
Finished Jun 02 01:43:15 PM PDT 24
Peak memory 196540 kb
Host smart-df3c4856-88cb-47fe-89d2-ff67ddc2fdbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202658866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2202658866
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.741272718
Short name T461
Test name
Test status
Simulation time 196870289 ps
CPU time 0.91 seconds
Started Jun 02 01:43:13 PM PDT 24
Finished Jun 02 01:43:14 PM PDT 24
Peak memory 196744 kb
Host smart-3d8b76f4-e5c8-4e4f-9898-5297bf6af5f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741272718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.741272718
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.128363438
Short name T66
Test name
Test status
Simulation time 60273417 ps
CPU time 2.01 seconds
Started Jun 02 01:43:16 PM PDT 24
Finished Jun 02 01:43:18 PM PDT 24
Peak memory 197944 kb
Host smart-9a0ea7ae-376d-4dc3-90b1-98553b1c2043
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128363438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.128363438
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.463701169
Short name T63
Test name
Test status
Simulation time 91856993 ps
CPU time 2.73 seconds
Started Jun 02 01:43:11 PM PDT 24
Finished Jun 02 01:43:14 PM PDT 24
Peak memory 196452 kb
Host smart-025a5dc7-3d2c-43d5-850b-f29f5cad3d2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463701169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
463701169
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3432505366
Short name T608
Test name
Test status
Simulation time 72356850 ps
CPU time 0.69 seconds
Started Jun 02 01:43:13 PM PDT 24
Finished Jun 02 01:43:14 PM PDT 24
Peak memory 194380 kb
Host smart-802d82e1-0602-40f1-bc6b-680670fd7450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432505366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3432505366
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2836764704
Short name T342
Test name
Test status
Simulation time 44800850 ps
CPU time 0.7 seconds
Started Jun 02 01:43:14 PM PDT 24
Finished Jun 02 01:43:15 PM PDT 24
Peak memory 195364 kb
Host smart-d8062722-08b3-431b-83d2-9791a4540de6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836764704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2836764704
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.859062328
Short name T69
Test name
Test status
Simulation time 107362058 ps
CPU time 2.05 seconds
Started Jun 02 01:43:18 PM PDT 24
Finished Jun 02 01:43:20 PM PDT 24
Peak memory 197996 kb
Host smart-cc30fc55-e9cc-4351-9f91-2f35c88d7d0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859062328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.859062328
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.666594872
Short name T411
Test name
Test status
Simulation time 77408795 ps
CPU time 1.25 seconds
Started Jun 02 01:43:16 PM PDT 24
Finished Jun 02 01:43:18 PM PDT 24
Peak memory 196288 kb
Host smart-39827546-01d2-4dfd-a90e-afa7549fb2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666594872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.666594872
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.4074770505
Short name T124
Test name
Test status
Simulation time 55218945 ps
CPU time 1.21 seconds
Started Jun 02 01:43:14 PM PDT 24
Finished Jun 02 01:43:15 PM PDT 24
Peak memory 195688 kb
Host smart-62dcd3b4-1796-417b-b5c3-0f835309d701
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074770505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.4074770505
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2334986525
Short name T527
Test name
Test status
Simulation time 2241300973 ps
CPU time 30.73 seconds
Started Jun 02 01:43:13 PM PDT 24
Finished Jun 02 01:43:45 PM PDT 24
Peak memory 198100 kb
Host smart-3d1f1553-36dd-4fcf-b7b1-04f0fe1d7e6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334986525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2334986525
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.57546362
Short name T27
Test name
Test status
Simulation time 107307044165 ps
CPU time 2060.04 seconds
Started Jun 02 01:43:18 PM PDT 24
Finished Jun 02 02:17:39 PM PDT 24
Peak memory 198188 kb
Host smart-9c5f4537-505f-4bd7-9cc7-a9bef6cced6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=57546362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.57546362
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.1275720721
Short name T451
Test name
Test status
Simulation time 13069053 ps
CPU time 0.57 seconds
Started Jun 02 01:43:13 PM PDT 24
Finished Jun 02 01:43:14 PM PDT 24
Peak memory 193836 kb
Host smart-d22f8a1a-af1a-48ed-aad4-a9eb28073418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275720721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1275720721
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2199405954
Short name T339
Test name
Test status
Simulation time 44328223 ps
CPU time 0.94 seconds
Started Jun 02 01:43:14 PM PDT 24
Finished Jun 02 01:43:15 PM PDT 24
Peak memory 195968 kb
Host smart-42ccf52e-fd88-4dd9-9245-a3717d02e3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199405954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2199405954
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.4160354206
Short name T25
Test name
Test status
Simulation time 264376181 ps
CPU time 9.48 seconds
Started Jun 02 01:43:11 PM PDT 24
Finished Jun 02 01:43:21 PM PDT 24
Peak memory 195500 kb
Host smart-db1eca0a-e705-455b-93fd-815b3f04d160
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160354206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.4160354206
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.4070720442
Short name T48
Test name
Test status
Simulation time 212490664 ps
CPU time 0.97 seconds
Started Jun 02 01:43:12 PM PDT 24
Finished Jun 02 01:43:13 PM PDT 24
Peak memory 197900 kb
Host smart-18c79b17-7a8a-4cfa-a7a0-ee3e88362498
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070720442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.4070720442
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1085102406
Short name T452
Test name
Test status
Simulation time 265290360 ps
CPU time 1.34 seconds
Started Jun 02 01:43:16 PM PDT 24
Finished Jun 02 01:43:18 PM PDT 24
Peak memory 195796 kb
Host smart-d9efa6e5-0858-4a8c-bc2d-378742312601
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085102406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1085102406
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3507327224
Short name T107
Test name
Test status
Simulation time 37074323 ps
CPU time 0.92 seconds
Started Jun 02 01:43:14 PM PDT 24
Finished Jun 02 01:43:15 PM PDT 24
Peak memory 196048 kb
Host smart-bf021aa1-3dbe-41a3-a1eb-db56203b8e07
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507327224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3507327224
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.4043330980
Short name T347
Test name
Test status
Simulation time 114548088 ps
CPU time 2.69 seconds
Started Jun 02 01:43:13 PM PDT 24
Finished Jun 02 01:43:16 PM PDT 24
Peak memory 195772 kb
Host smart-224b7a33-a6dc-4331-9163-0fe754219feb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043330980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.4043330980
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.848248661
Short name T502
Test name
Test status
Simulation time 32638897 ps
CPU time 0.79 seconds
Started Jun 02 01:43:17 PM PDT 24
Finished Jun 02 01:43:18 PM PDT 24
Peak memory 196064 kb
Host smart-50dce65e-56e9-4a82-9528-086a02829492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848248661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.848248661
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2539556449
Short name T381
Test name
Test status
Simulation time 95644832 ps
CPU time 1.05 seconds
Started Jun 02 01:43:15 PM PDT 24
Finished Jun 02 01:43:17 PM PDT 24
Peak memory 195960 kb
Host smart-6445715c-8667-40f9-b924-f8f1528384e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539556449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2539556449
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3992872817
Short name T2
Test name
Test status
Simulation time 1317831679 ps
CPU time 4.82 seconds
Started Jun 02 01:43:16 PM PDT 24
Finished Jun 02 01:43:21 PM PDT 24
Peak memory 197948 kb
Host smart-74940cf4-a907-4006-b16a-2bb92727cd6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992872817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3992872817
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3090789985
Short name T254
Test name
Test status
Simulation time 151845654 ps
CPU time 1.41 seconds
Started Jun 02 01:43:17 PM PDT 24
Finished Jun 02 01:43:19 PM PDT 24
Peak memory 197888 kb
Host smart-b721dd2c-4d8a-48ec-b2c1-f8b204b5af93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090789985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3090789985
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3379839095
Short name T209
Test name
Test status
Simulation time 28195517 ps
CPU time 0.87 seconds
Started Jun 02 01:43:18 PM PDT 24
Finished Jun 02 01:43:19 PM PDT 24
Peak memory 195952 kb
Host smart-d406ad89-3d39-49af-8aca-c66f0ad4cb19
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379839095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3379839095
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.589242272
Short name T8
Test name
Test status
Simulation time 21177099668 ps
CPU time 236.81 seconds
Started Jun 02 01:43:14 PM PDT 24
Finished Jun 02 01:47:11 PM PDT 24
Peak memory 198216 kb
Host smart-2dd06780-fd9f-47e3-b8c0-9aa15ba2c323
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589242272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.589242272
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.1627144797
Short name T55
Test name
Test status
Simulation time 17452531043 ps
CPU time 491.48 seconds
Started Jun 02 01:43:16 PM PDT 24
Finished Jun 02 01:51:28 PM PDT 24
Peak memory 198248 kb
Host smart-8dfbdead-ebaa-4e75-ae73-8956b187fa84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1627144797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.1627144797
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.4223014755
Short name T230
Test name
Test status
Simulation time 12873742 ps
CPU time 0.57 seconds
Started Jun 02 01:43:19 PM PDT 24
Finished Jun 02 01:43:20 PM PDT 24
Peak memory 194108 kb
Host smart-33b7623f-e2a3-4cdb-8e05-809d92ec0d4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223014755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.4223014755
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.461059528
Short name T253
Test name
Test status
Simulation time 47295130 ps
CPU time 0.95 seconds
Started Jun 02 01:43:22 PM PDT 24
Finished Jun 02 01:43:24 PM PDT 24
Peak memory 195684 kb
Host smart-5f7d6e0b-6d36-4900-a848-9c5c6c9a04b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461059528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.461059528
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.3430684317
Short name T121
Test name
Test status
Simulation time 319636969 ps
CPU time 10.07 seconds
Started Jun 02 01:43:22 PM PDT 24
Finished Jun 02 01:43:33 PM PDT 24
Peak memory 195676 kb
Host smart-e78b50f1-236d-4b41-815f-c9a62281c3d9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430684317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.3430684317
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3518213414
Short name T433
Test name
Test status
Simulation time 88505674 ps
CPU time 0.97 seconds
Started Jun 02 01:43:23 PM PDT 24
Finished Jun 02 01:43:24 PM PDT 24
Peak memory 197684 kb
Host smart-241891d7-d50e-48da-b2ff-55dc609ebe89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518213414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3518213414
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.791052635
Short name T240
Test name
Test status
Simulation time 548867368 ps
CPU time 1.46 seconds
Started Jun 02 01:43:20 PM PDT 24
Finished Jun 02 01:43:22 PM PDT 24
Peak memory 197996 kb
Host smart-7a2f1a76-e17f-44d5-ae74-a09c9047ffa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791052635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.791052635
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3882326633
Short name T639
Test name
Test status
Simulation time 60224524 ps
CPU time 2.46 seconds
Started Jun 02 01:43:19 PM PDT 24
Finished Jun 02 01:43:22 PM PDT 24
Peak memory 197992 kb
Host smart-3abc5c08-82cd-40fa-be59-f1c5843ffb5a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882326633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3882326633
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3089397887
Short name T553
Test name
Test status
Simulation time 303005347 ps
CPU time 2.3 seconds
Started Jun 02 01:43:21 PM PDT 24
Finished Jun 02 01:43:23 PM PDT 24
Peak memory 198044 kb
Host smart-d2eb6bf1-c767-4b6e-beb5-9d580d00fa96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089397887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3089397887
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.513507722
Short name T338
Test name
Test status
Simulation time 51153962 ps
CPU time 1 seconds
Started Jun 02 01:43:20 PM PDT 24
Finished Jun 02 01:43:21 PM PDT 24
Peak memory 195960 kb
Host smart-5af2cfc3-445a-4b43-9cdf-d4ae0ef6888b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513507722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.513507722
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1479635219
Short name T190
Test name
Test status
Simulation time 23494508 ps
CPU time 0.75 seconds
Started Jun 02 01:43:19 PM PDT 24
Finished Jun 02 01:43:20 PM PDT 24
Peak memory 196048 kb
Host smart-3ad8689c-f9cc-4367-a202-7cfd19fae14d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479635219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1479635219
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1827913758
Short name T648
Test name
Test status
Simulation time 341168565 ps
CPU time 1.57 seconds
Started Jun 02 01:43:20 PM PDT 24
Finished Jun 02 01:43:22 PM PDT 24
Peak memory 197972 kb
Host smart-2b8003df-5c5f-4baf-8780-8d282d900b61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827913758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1827913758
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.817484911
Short name T177
Test name
Test status
Simulation time 71212842 ps
CPU time 1.33 seconds
Started Jun 02 01:43:12 PM PDT 24
Finished Jun 02 01:43:14 PM PDT 24
Peak memory 195500 kb
Host smart-70bb1e9c-19a9-4169-b7ba-4fcc00a7b441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817484911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.817484911
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2897324092
Short name T390
Test name
Test status
Simulation time 437740624 ps
CPU time 0.93 seconds
Started Jun 02 01:43:16 PM PDT 24
Finished Jun 02 01:43:17 PM PDT 24
Peak memory 195344 kb
Host smart-05627130-4ae5-4140-a7ec-42b30617ba71
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897324092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2897324092
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1391333469
Short name T297
Test name
Test status
Simulation time 5889224407 ps
CPU time 108.87 seconds
Started Jun 02 01:43:22 PM PDT 24
Finished Jun 02 01:45:12 PM PDT 24
Peak memory 198148 kb
Host smart-a7287391-03b7-4c5a-8558-ad64a27731a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391333469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1391333469
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2547839851
Short name T585
Test name
Test status
Simulation time 919851915945 ps
CPU time 2448.52 seconds
Started Jun 02 01:43:20 PM PDT 24
Finished Jun 02 02:24:09 PM PDT 24
Peak memory 206440 kb
Host smart-08df4f22-6220-4ff4-8307-5ab9bf54251b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2547839851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2547839851
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2001044384
Short name T270
Test name
Test status
Simulation time 11560378 ps
CPU time 0.59 seconds
Started Jun 02 01:43:21 PM PDT 24
Finished Jun 02 01:43:22 PM PDT 24
Peak memory 193840 kb
Host smart-59d285de-b1e9-42ad-a7dc-81a343b380a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001044384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2001044384
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.936558725
Short name T12
Test name
Test status
Simulation time 172590590 ps
CPU time 0.86 seconds
Started Jun 02 01:43:21 PM PDT 24
Finished Jun 02 01:43:22 PM PDT 24
Peak memory 197152 kb
Host smart-26077ddc-f3cc-4378-a9c1-cf0bdbe3554f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936558725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.936558725
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1808353176
Short name T634
Test name
Test status
Simulation time 688187948 ps
CPU time 24.49 seconds
Started Jun 02 01:43:21 PM PDT 24
Finished Jun 02 01:43:46 PM PDT 24
Peak memory 196248 kb
Host smart-159da1da-41fb-436f-8fa0-0f90ffb6d20d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808353176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1808353176
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1858573097
Short name T498
Test name
Test status
Simulation time 799092089 ps
CPU time 0.98 seconds
Started Jun 02 01:43:22 PM PDT 24
Finished Jun 02 01:43:23 PM PDT 24
Peak memory 197768 kb
Host smart-1de7249d-254e-4d1f-9e3c-6d21a9b03fa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858573097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1858573097
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.596644488
Short name T667
Test name
Test status
Simulation time 610455753 ps
CPU time 1.1 seconds
Started Jun 02 01:43:20 PM PDT 24
Finished Jun 02 01:43:22 PM PDT 24
Peak memory 196088 kb
Host smart-be5e3a38-bce5-405c-992e-1cd809fe590e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596644488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.596644488
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1187224183
Short name T473
Test name
Test status
Simulation time 1341877289 ps
CPU time 3.25 seconds
Started Jun 02 01:43:22 PM PDT 24
Finished Jun 02 01:43:26 PM PDT 24
Peak memory 198036 kb
Host smart-425ccd7e-26ac-442f-a7f1-bcba9591d2c9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187224183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1187224183
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.102590147
Short name T194
Test name
Test status
Simulation time 115076068 ps
CPU time 2.55 seconds
Started Jun 02 01:43:20 PM PDT 24
Finished Jun 02 01:43:23 PM PDT 24
Peak memory 197168 kb
Host smart-48d1bf70-eb7e-433a-8a6f-dec1606b78fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102590147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
102590147
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3083581615
Short name T74
Test name
Test status
Simulation time 66983941 ps
CPU time 0.87 seconds
Started Jun 02 01:43:21 PM PDT 24
Finished Jun 02 01:43:22 PM PDT 24
Peak memory 195952 kb
Host smart-f3da3859-ef98-4dfb-985f-db21d8b28b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083581615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3083581615
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.282981031
Short name T53
Test name
Test status
Simulation time 36410663 ps
CPU time 0.87 seconds
Started Jun 02 01:43:19 PM PDT 24
Finished Jun 02 01:43:20 PM PDT 24
Peak memory 195444 kb
Host smart-6fa06517-1734-4073-8774-bff1cc44d68d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282981031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.282981031
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2134166728
Short name T378
Test name
Test status
Simulation time 67697758 ps
CPU time 2.88 seconds
Started Jun 02 01:43:21 PM PDT 24
Finished Jun 02 01:43:24 PM PDT 24
Peak memory 197892 kb
Host smart-d3ba88de-58f5-4c0d-9784-0acc8030ccaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134166728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2134166728
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.192445238
Short name T67
Test name
Test status
Simulation time 137722961 ps
CPU time 1.4 seconds
Started Jun 02 01:43:21 PM PDT 24
Finished Jun 02 01:43:23 PM PDT 24
Peak memory 195576 kb
Host smart-8af4b5fb-1708-4a52-9410-61f8235bf861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192445238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.192445238
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3135866406
Short name T546
Test name
Test status
Simulation time 23360471 ps
CPU time 0.74 seconds
Started Jun 02 01:43:21 PM PDT 24
Finished Jun 02 01:43:22 PM PDT 24
Peak memory 195868 kb
Host smart-af1a4b20-8f16-4cb0-9bd8-d4ad8aef0837
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135866406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3135866406
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2791210697
Short name T683
Test name
Test status
Simulation time 6601306935 ps
CPU time 72.56 seconds
Started Jun 02 01:43:19 PM PDT 24
Finished Jun 02 01:44:32 PM PDT 24
Peak memory 198132 kb
Host smart-cbd2042a-a15a-4979-aee9-1fc94057c6d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791210697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2791210697
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1324339549
Short name T296
Test name
Test status
Simulation time 18762571 ps
CPU time 0.57 seconds
Started Jun 02 01:43:27 PM PDT 24
Finished Jun 02 01:43:28 PM PDT 24
Peak memory 193860 kb
Host smart-d1c00083-bf53-48f4-9d6c-84388e8093f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324339549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1324339549
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2028659710
Short name T282
Test name
Test status
Simulation time 41797159 ps
CPU time 0.9 seconds
Started Jun 02 01:43:18 PM PDT 24
Finished Jun 02 01:43:19 PM PDT 24
Peak memory 196528 kb
Host smart-9c5e6545-83d7-481b-b59d-2fa4ea178b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028659710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2028659710
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3292126967
Short name T508
Test name
Test status
Simulation time 1612070005 ps
CPU time 14.33 seconds
Started Jun 02 01:43:26 PM PDT 24
Finished Jun 02 01:43:41 PM PDT 24
Peak memory 195520 kb
Host smart-246cdbcd-0685-4c52-bd82-faaa03f30eff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292126967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3292126967
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2089484973
Short name T525
Test name
Test status
Simulation time 133166569 ps
CPU time 1 seconds
Started Jun 02 01:43:25 PM PDT 24
Finished Jun 02 01:43:27 PM PDT 24
Peak memory 197720 kb
Host smart-4229c29d-0388-4580-acf9-a52fff28394f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089484973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2089484973
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.172428336
Short name T652
Test name
Test status
Simulation time 74780942 ps
CPU time 1.13 seconds
Started Jun 02 01:43:26 PM PDT 24
Finished Jun 02 01:43:28 PM PDT 24
Peak memory 195980 kb
Host smart-09c962bc-ec4a-4f3b-9289-a2990f957331
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172428336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.172428336
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.409774214
Short name T391
Test name
Test status
Simulation time 21472144 ps
CPU time 0.93 seconds
Started Jun 02 01:43:30 PM PDT 24
Finished Jun 02 01:43:31 PM PDT 24
Peak memory 195952 kb
Host smart-1675d15b-381c-4051-93ba-b50e51c33a3a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409774214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.409774214
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.581838292
Short name T574
Test name
Test status
Simulation time 284329732 ps
CPU time 3.3 seconds
Started Jun 02 01:43:25 PM PDT 24
Finished Jun 02 01:43:29 PM PDT 24
Peak memory 196788 kb
Host smart-075c6935-8252-4cc2-a24e-e5e489c60f18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581838292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
581838292
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2834998195
Short name T249
Test name
Test status
Simulation time 45010459 ps
CPU time 0.95 seconds
Started Jun 02 01:43:21 PM PDT 24
Finished Jun 02 01:43:22 PM PDT 24
Peak memory 196680 kb
Host smart-3b062799-3589-419c-8f72-d630b4576ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834998195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2834998195
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3660062166
Short name T192
Test name
Test status
Simulation time 43269914 ps
CPU time 0.87 seconds
Started Jun 02 01:43:20 PM PDT 24
Finished Jun 02 01:43:22 PM PDT 24
Peak memory 195836 kb
Host smart-a128e0a1-0c11-46a9-9dcb-358884a1d079
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660062166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3660062166
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.430334558
Short name T503
Test name
Test status
Simulation time 563780022 ps
CPU time 6.56 seconds
Started Jun 02 01:43:26 PM PDT 24
Finished Jun 02 01:43:33 PM PDT 24
Peak memory 197680 kb
Host smart-0cc30900-1d4a-496e-8178-1dee5e325792
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430334558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.430334558
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.1331254893
Short name T73
Test name
Test status
Simulation time 85483110 ps
CPU time 0.97 seconds
Started Jun 02 01:43:22 PM PDT 24
Finished Jun 02 01:43:24 PM PDT 24
Peak memory 195756 kb
Host smart-dbf3ac96-5039-444d-a6ad-4b3b3e36066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331254893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1331254893
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1658119560
Short name T701
Test name
Test status
Simulation time 90299304 ps
CPU time 1.48 seconds
Started Jun 02 01:43:21 PM PDT 24
Finished Jun 02 01:43:23 PM PDT 24
Peak memory 196760 kb
Host smart-25e20cde-07ef-4ab5-8e8d-b209d76fe393
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658119560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1658119560
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.443446334
Short name T286
Test name
Test status
Simulation time 14946501659 ps
CPU time 43.26 seconds
Started Jun 02 01:43:24 PM PDT 24
Finished Jun 02 01:44:08 PM PDT 24
Peak memory 198176 kb
Host smart-2944a4f0-1389-4ffb-a603-f3f580cd8c58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443446334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.443446334
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.3402387146
Short name T612
Test name
Test status
Simulation time 104945709218 ps
CPU time 2228.44 seconds
Started Jun 02 01:43:25 PM PDT 24
Finished Jun 02 02:20:34 PM PDT 24
Peak memory 198216 kb
Host smart-1641eb43-195d-46da-b886-ca98cbd0dce9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3402387146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.3402387146
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2758151325
Short name T409
Test name
Test status
Simulation time 24160922 ps
CPU time 0.6 seconds
Started Jun 02 01:43:28 PM PDT 24
Finished Jun 02 01:43:28 PM PDT 24
Peak memory 193780 kb
Host smart-954cb4f6-239f-42ba-b349-830ce38d3073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758151325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2758151325
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3701676173
Short name T428
Test name
Test status
Simulation time 48042886 ps
CPU time 0.92 seconds
Started Jun 02 01:43:27 PM PDT 24
Finished Jun 02 01:43:28 PM PDT 24
Peak memory 197368 kb
Host smart-9609d00b-44d5-4062-8911-06ba8ae90c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701676173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3701676173
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2999473563
Short name T366
Test name
Test status
Simulation time 273387033 ps
CPU time 14.51 seconds
Started Jun 02 01:43:26 PM PDT 24
Finished Jun 02 01:43:41 PM PDT 24
Peak memory 197964 kb
Host smart-3f843ea3-00b4-4d52-937e-b727e5547804
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999473563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2999473563
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1064527903
Short name T564
Test name
Test status
Simulation time 156365945 ps
CPU time 0.85 seconds
Started Jun 02 01:43:30 PM PDT 24
Finished Jun 02 01:43:31 PM PDT 24
Peak memory 197132 kb
Host smart-21d61506-91c6-44da-ab4a-020b7257c827
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064527903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1064527903
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2382455949
Short name T429
Test name
Test status
Simulation time 28921639 ps
CPU time 0.79 seconds
Started Jun 02 01:43:28 PM PDT 24
Finished Jun 02 01:43:29 PM PDT 24
Peak memory 195384 kb
Host smart-62cd85ed-bbeb-4914-8aaf-5c3de2356039
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382455949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2382455949
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.709601885
Short name T384
Test name
Test status
Simulation time 25205076 ps
CPU time 1.06 seconds
Started Jun 02 01:43:30 PM PDT 24
Finished Jun 02 01:43:31 PM PDT 24
Peak memory 196400 kb
Host smart-6d839833-531c-4c28-b857-fae5600aaebf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709601885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.709601885
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.4005663840
Short name T238
Test name
Test status
Simulation time 536393294 ps
CPU time 2.86 seconds
Started Jun 02 01:43:29 PM PDT 24
Finished Jun 02 01:43:33 PM PDT 24
Peak memory 196728 kb
Host smart-2549610f-0675-45fe-8358-ffa5bd90b14b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005663840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.4005663840
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.4003634982
Short name T139
Test name
Test status
Simulation time 23570819 ps
CPU time 0.85 seconds
Started Jun 02 01:43:25 PM PDT 24
Finished Jun 02 01:43:26 PM PDT 24
Peak memory 195812 kb
Host smart-9e3f6a67-fcbc-4941-908b-2d5baa782e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003634982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.4003634982
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3578075812
Short name T150
Test name
Test status
Simulation time 30290840 ps
CPU time 0.77 seconds
Started Jun 02 01:43:25 PM PDT 24
Finished Jun 02 01:43:26 PM PDT 24
Peak memory 196200 kb
Host smart-a5c41693-6d46-47da-abe4-26c008f5014d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578075812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3578075812
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.385156647
Short name T7
Test name
Test status
Simulation time 503780740 ps
CPU time 6.12 seconds
Started Jun 02 01:43:25 PM PDT 24
Finished Jun 02 01:43:32 PM PDT 24
Peak memory 197952 kb
Host smart-dcbbaf60-3cfb-428c-a6f2-678cf7fbb3f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385156647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran
dom_long_reg_writes_reg_reads.385156647
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2483495925
Short name T624
Test name
Test status
Simulation time 305552535 ps
CPU time 1.25 seconds
Started Jun 02 01:43:25 PM PDT 24
Finished Jun 02 01:43:26 PM PDT 24
Peak memory 195776 kb
Host smart-bf0efcb0-a3b5-4998-9e36-1236b0a3b0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483495925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2483495925
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2608535856
Short name T423
Test name
Test status
Simulation time 75245270 ps
CPU time 1.2 seconds
Started Jun 02 01:43:30 PM PDT 24
Finished Jun 02 01:43:31 PM PDT 24
Peak memory 196704 kb
Host smart-36b8396a-3f31-4eac-8587-36e16b200175
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608535856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2608535856
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3705723577
Short name T362
Test name
Test status
Simulation time 52908742 ps
CPU time 0.59 seconds
Started Jun 02 01:43:31 PM PDT 24
Finished Jun 02 01:43:33 PM PDT 24
Peak memory 194808 kb
Host smart-f12065ee-9542-4f1d-a259-bc9ad5edc98c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705723577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3705723577
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1969894222
Short name T277
Test name
Test status
Simulation time 146594478 ps
CPU time 0.95 seconds
Started Jun 02 01:43:26 PM PDT 24
Finished Jun 02 01:43:27 PM PDT 24
Peak memory 196572 kb
Host smart-07b2f158-76b1-4fc7-8d22-b455d39c177b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969894222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1969894222
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3569668873
Short name T212
Test name
Test status
Simulation time 1690811763 ps
CPU time 21.96 seconds
Started Jun 02 01:43:33 PM PDT 24
Finished Jun 02 01:43:55 PM PDT 24
Peak memory 196564 kb
Host smart-41b1de62-5ed8-44a6-8498-e32a93b37b7c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569668873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3569668873
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.524368332
Short name T398
Test name
Test status
Simulation time 218629224 ps
CPU time 0.83 seconds
Started Jun 02 01:43:36 PM PDT 24
Finished Jun 02 01:43:38 PM PDT 24
Peak memory 195888 kb
Host smart-c8b48a1d-d73c-490c-b0ad-59d65c2e08ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524368332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.524368332
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2018014881
Short name T145
Test name
Test status
Simulation time 29780999 ps
CPU time 0.7 seconds
Started Jun 02 01:43:36 PM PDT 24
Finished Jun 02 01:43:37 PM PDT 24
Peak memory 194304 kb
Host smart-10d34fe4-899d-4d1f-998f-032d8dedf58f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018014881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2018014881
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1641234125
Short name T341
Test name
Test status
Simulation time 84380081 ps
CPU time 3.44 seconds
Started Jun 02 01:43:33 PM PDT 24
Finished Jun 02 01:43:37 PM PDT 24
Peak memory 198000 kb
Host smart-a8d65f5d-7130-4ebd-8429-a2ee7ac5a069
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641234125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1641234125
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1450511152
Short name T351
Test name
Test status
Simulation time 162387113 ps
CPU time 1.97 seconds
Started Jun 02 01:43:32 PM PDT 24
Finished Jun 02 01:43:35 PM PDT 24
Peak memory 195872 kb
Host smart-3d884a72-b2e6-4acb-8ae1-e8915ca08cfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450511152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1450511152
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.685938555
Short name T132
Test name
Test status
Simulation time 20057097 ps
CPU time 0.83 seconds
Started Jun 02 01:43:26 PM PDT 24
Finished Jun 02 01:43:27 PM PDT 24
Peak memory 195396 kb
Host smart-5a738591-5989-44e9-b502-0b5d7ac3bd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685938555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.685938555
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.539003558
Short name T544
Test name
Test status
Simulation time 71886742 ps
CPU time 0.93 seconds
Started Jun 02 01:43:26 PM PDT 24
Finished Jun 02 01:43:28 PM PDT 24
Peak memory 196856 kb
Host smart-eb379994-96bd-4526-b187-4386c6bbe77e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539003558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.539003558
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1650628373
Short name T697
Test name
Test status
Simulation time 939817277 ps
CPU time 3.23 seconds
Started Jun 02 01:43:32 PM PDT 24
Finished Jun 02 01:43:36 PM PDT 24
Peak memory 197940 kb
Host smart-d44ba61d-2134-4508-a4b1-d913d4f78c94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650628373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1650628373
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.506346839
Short name T408
Test name
Test status
Simulation time 227274906 ps
CPU time 1.24 seconds
Started Jun 02 01:43:32 PM PDT 24
Finished Jun 02 01:43:34 PM PDT 24
Peak memory 196932 kb
Host smart-7b99d7ce-5b1e-4b67-858b-9c8feab53ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506346839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.506346839
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2669928446
Short name T611
Test name
Test status
Simulation time 782064875 ps
CPU time 1.29 seconds
Started Jun 02 01:43:32 PM PDT 24
Finished Jun 02 01:43:34 PM PDT 24
Peak memory 196732 kb
Host smart-f144d2cb-f68a-4d49-9001-81322cee8ff6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669928446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2669928446
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1675452595
Short name T152
Test name
Test status
Simulation time 3894385367 ps
CPU time 49.16 seconds
Started Jun 02 01:43:34 PM PDT 24
Finished Jun 02 01:44:24 PM PDT 24
Peak memory 198092 kb
Host smart-787c325d-9078-4b2f-9ae5-0c9ca514de38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675452595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1675452595
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.27583006
Short name T549
Test name
Test status
Simulation time 50019437 ps
CPU time 0.59 seconds
Started Jun 02 01:43:38 PM PDT 24
Finished Jun 02 01:43:40 PM PDT 24
Peak memory 194068 kb
Host smart-937b9dc5-c3b3-4207-934e-0f6646873d10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27583006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.27583006
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.630425849
Short name T465
Test name
Test status
Simulation time 35961266 ps
CPU time 0.82 seconds
Started Jun 02 01:43:31 PM PDT 24
Finished Jun 02 01:43:33 PM PDT 24
Peak memory 195392 kb
Host smart-1510b5eb-92ea-4399-9173-7f63f48a932c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630425849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.630425849
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1981943134
Short name T552
Test name
Test status
Simulation time 1756438427 ps
CPU time 24.09 seconds
Started Jun 02 01:43:33 PM PDT 24
Finished Jun 02 01:43:58 PM PDT 24
Peak memory 196888 kb
Host smart-14152ba8-662e-4d6a-bc1f-c6b0f5a6d382
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981943134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1981943134
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1366763686
Short name T551
Test name
Test status
Simulation time 311748654 ps
CPU time 1.14 seconds
Started Jun 02 01:43:40 PM PDT 24
Finished Jun 02 01:43:42 PM PDT 24
Peak memory 197980 kb
Host smart-733d5dea-ed93-4c77-a31c-d924517dc178
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366763686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1366763686
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3734017447
Short name T520
Test name
Test status
Simulation time 107582377 ps
CPU time 1.5 seconds
Started Jun 02 01:43:32 PM PDT 24
Finished Jun 02 01:43:34 PM PDT 24
Peak memory 197020 kb
Host smart-149fc1bf-f3be-4652-934f-f3adf888f4ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734017447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3734017447
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2222509724
Short name T490
Test name
Test status
Simulation time 48534357 ps
CPU time 1.91 seconds
Started Jun 02 01:43:35 PM PDT 24
Finished Jun 02 01:43:37 PM PDT 24
Peak memory 198048 kb
Host smart-af9081a0-06d6-499e-9e83-e35b7cc86d22
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222509724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2222509724
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.302117275
Short name T352
Test name
Test status
Simulation time 233876724 ps
CPU time 3.42 seconds
Started Jun 02 01:43:34 PM PDT 24
Finished Jun 02 01:43:38 PM PDT 24
Peak memory 197060 kb
Host smart-f8478de2-0cc3-462d-8d2f-9d5ece4063d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302117275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
302117275
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.239839247
Short name T380
Test name
Test status
Simulation time 45414255 ps
CPU time 0.97 seconds
Started Jun 02 01:43:33 PM PDT 24
Finished Jun 02 01:43:34 PM PDT 24
Peak memory 196532 kb
Host smart-60b92d29-af0e-498d-bfbf-697cfaf43d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239839247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.239839247
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.263222534
Short name T213
Test name
Test status
Simulation time 26485152 ps
CPU time 1.04 seconds
Started Jun 02 01:43:32 PM PDT 24
Finished Jun 02 01:43:34 PM PDT 24
Peak memory 196728 kb
Host smart-865d2f9a-21a2-474c-a45b-149edf21f087
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263222534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.263222534
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2230752400
Short name T257
Test name
Test status
Simulation time 1097286127 ps
CPU time 4.59 seconds
Started Jun 02 01:43:37 PM PDT 24
Finished Jun 02 01:43:43 PM PDT 24
Peak memory 197928 kb
Host smart-b59b6162-4bbc-46b2-a0f8-3d08abbc0b06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230752400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2230752400
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3014715620
Short name T420
Test name
Test status
Simulation time 143298775 ps
CPU time 1.37 seconds
Started Jun 02 01:43:32 PM PDT 24
Finished Jun 02 01:43:34 PM PDT 24
Peak memory 196208 kb
Host smart-3bd91f73-b1ed-4e14-aefa-735b1b4008e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014715620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3014715620
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2065397184
Short name T371
Test name
Test status
Simulation time 286352443 ps
CPU time 1.36 seconds
Started Jun 02 01:43:37 PM PDT 24
Finished Jun 02 01:43:39 PM PDT 24
Peak memory 196756 kb
Host smart-ccff7565-4bf6-43c8-8ab1-f90beb9e74c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065397184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2065397184
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1344646177
Short name T647
Test name
Test status
Simulation time 1761373684 ps
CPU time 26.36 seconds
Started Jun 02 01:43:38 PM PDT 24
Finished Jun 02 01:44:05 PM PDT 24
Peak memory 198040 kb
Host smart-fb69013a-ac2b-4f77-9d6b-68225d95d9cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344646177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1344646177
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2020806368
Short name T616
Test name
Test status
Simulation time 11897730 ps
CPU time 0.56 seconds
Started Jun 02 01:43:39 PM PDT 24
Finished Jun 02 01:43:40 PM PDT 24
Peak memory 194528 kb
Host smart-86f6cbaa-555c-42ee-9eaa-c97e7f652687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020806368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2020806368
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2248834332
Short name T570
Test name
Test status
Simulation time 32772287 ps
CPU time 0.92 seconds
Started Jun 02 01:43:38 PM PDT 24
Finished Jun 02 01:43:40 PM PDT 24
Peak memory 195804 kb
Host smart-85f97efc-ebbc-477f-85dd-b959be629874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248834332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2248834332
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.4130116371
Short name T65
Test name
Test status
Simulation time 387920474 ps
CPU time 13.21 seconds
Started Jun 02 01:43:38 PM PDT 24
Finished Jun 02 01:43:52 PM PDT 24
Peak memory 196260 kb
Host smart-c7a86b1f-ee69-402c-8754-6f93177d12b6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130116371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.4130116371
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3548973116
Short name T72
Test name
Test status
Simulation time 118411671 ps
CPU time 0.76 seconds
Started Jun 02 01:43:38 PM PDT 24
Finished Jun 02 01:43:39 PM PDT 24
Peak memory 194732 kb
Host smart-2736b53e-cb44-4566-8526-2b16a08a639f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548973116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3548973116
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.22836028
Short name T499
Test name
Test status
Simulation time 302826507 ps
CPU time 1.36 seconds
Started Jun 02 01:43:38 PM PDT 24
Finished Jun 02 01:43:40 PM PDT 24
Peak memory 198024 kb
Host smart-0e79d27c-1f96-445b-8a97-2d1145346b5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22836028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.22836028
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.4279407228
Short name T663
Test name
Test status
Simulation time 71032512 ps
CPU time 2.59 seconds
Started Jun 02 01:43:38 PM PDT 24
Finished Jun 02 01:43:42 PM PDT 24
Peak memory 196464 kb
Host smart-a7bdaafc-0d19-4792-acb3-d25e631d0346
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279407228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.4279407228
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1111028028
Short name T225
Test name
Test status
Simulation time 106464263 ps
CPU time 3.15 seconds
Started Jun 02 01:43:38 PM PDT 24
Finished Jun 02 01:43:42 PM PDT 24
Peak memory 197040 kb
Host smart-d88a490c-9540-4b20-84d1-42a3811faa84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111028028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1111028028
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.497905559
Short name T430
Test name
Test status
Simulation time 104831455 ps
CPU time 1.2 seconds
Started Jun 02 01:43:39 PM PDT 24
Finished Jun 02 01:43:41 PM PDT 24
Peak memory 197032 kb
Host smart-b221b453-1450-41c0-96a0-e6127b20706a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497905559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.497905559
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2081954589
Short name T14
Test name
Test status
Simulation time 28540284 ps
CPU time 0.86 seconds
Started Jun 02 01:43:40 PM PDT 24
Finished Jun 02 01:43:41 PM PDT 24
Peak memory 195512 kb
Host smart-35548c62-02b0-4661-9573-7f20de2d3106
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081954589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2081954589
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.614666233
Short name T470
Test name
Test status
Simulation time 59615574 ps
CPU time 1.42 seconds
Started Jun 02 01:43:39 PM PDT 24
Finished Jun 02 01:43:41 PM PDT 24
Peak memory 197908 kb
Host smart-ac2e9fa2-5334-4452-8d3c-cc9abaccdff7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614666233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.614666233
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3707844045
Short name T310
Test name
Test status
Simulation time 66624672 ps
CPU time 1.1 seconds
Started Jun 02 01:43:38 PM PDT 24
Finished Jun 02 01:43:40 PM PDT 24
Peak memory 195828 kb
Host smart-cf2aa09e-32a6-477a-b9c9-7e36f292873d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707844045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3707844045
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.804551030
Short name T655
Test name
Test status
Simulation time 237043072 ps
CPU time 1.18 seconds
Started Jun 02 01:43:39 PM PDT 24
Finished Jun 02 01:43:41 PM PDT 24
Peak memory 195920 kb
Host smart-a581f891-d36f-472a-8702-3dfd459b36a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804551030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.804551030
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3651038968
Short name T466
Test name
Test status
Simulation time 5209073437 ps
CPU time 126.11 seconds
Started Jun 02 01:43:40 PM PDT 24
Finished Jun 02 01:45:47 PM PDT 24
Peak memory 198144 kb
Host smart-1e31288e-0d85-4b7e-9e12-32225951c38e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651038968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3651038968
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.917461085
Short name T287
Test name
Test status
Simulation time 39241688 ps
CPU time 0.58 seconds
Started Jun 02 01:42:27 PM PDT 24
Finished Jun 02 01:42:29 PM PDT 24
Peak memory 193872 kb
Host smart-61fca427-337a-4080-a244-44143c155970
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917461085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.917461085
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.404129326
Short name T231
Test name
Test status
Simulation time 104250545 ps
CPU time 0.92 seconds
Started Jun 02 01:42:28 PM PDT 24
Finished Jun 02 01:42:30 PM PDT 24
Peak memory 196660 kb
Host smart-0503dd0f-52f2-4ec2-b966-0f252e6245fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404129326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.404129326
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1770416625
Short name T321
Test name
Test status
Simulation time 3019005716 ps
CPU time 25.77 seconds
Started Jun 02 01:42:28 PM PDT 24
Finished Jun 02 01:42:55 PM PDT 24
Peak memory 198400 kb
Host smart-0755efa9-05b4-4d96-8305-04254e0d98c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770416625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1770416625
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.983954417
Short name T219
Test name
Test status
Simulation time 31782338 ps
CPU time 0.71 seconds
Started Jun 02 01:42:29 PM PDT 24
Finished Jun 02 01:42:30 PM PDT 24
Peak memory 194632 kb
Host smart-86b0c723-6550-4031-9bc3-28ac50d4fd4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983954417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.983954417
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1596997321
Short name T298
Test name
Test status
Simulation time 76482467 ps
CPU time 1.26 seconds
Started Jun 02 01:42:27 PM PDT 24
Finished Jun 02 01:42:29 PM PDT 24
Peak memory 196452 kb
Host smart-36c096b8-7e5e-4a50-881f-124f63352216
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596997321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1596997321
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1400606803
Short name T226
Test name
Test status
Simulation time 121991514 ps
CPU time 1.25 seconds
Started Jun 02 01:42:27 PM PDT 24
Finished Jun 02 01:42:29 PM PDT 24
Peak memory 196240 kb
Host smart-6b5cb397-a141-45e1-9b9f-ed68a9fb423d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400606803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1400606803
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2756111526
Short name T71
Test name
Test status
Simulation time 51634362 ps
CPU time 1.2 seconds
Started Jun 02 01:42:28 PM PDT 24
Finished Jun 02 01:42:30 PM PDT 24
Peak memory 196840 kb
Host smart-324bba65-1cde-4f6a-869c-4d278f2e54f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756111526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2756111526
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1359042416
Short name T714
Test name
Test status
Simulation time 181389057 ps
CPU time 1.08 seconds
Started Jun 02 01:42:25 PM PDT 24
Finished Jun 02 01:42:26 PM PDT 24
Peak memory 196088 kb
Host smart-b62317c5-8cc7-4594-a8c6-70c10458e830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359042416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1359042416
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2311357189
Short name T705
Test name
Test status
Simulation time 26852312 ps
CPU time 1.07 seconds
Started Jun 02 01:42:22 PM PDT 24
Finished Jun 02 01:42:24 PM PDT 24
Peak memory 196024 kb
Host smart-0c99e525-f883-48c4-b1d2-d83756e8fb8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311357189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2311357189
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2494376036
Short name T597
Test name
Test status
Simulation time 349433460 ps
CPU time 4.06 seconds
Started Jun 02 01:42:30 PM PDT 24
Finished Jun 02 01:42:34 PM PDT 24
Peak memory 197960 kb
Host smart-274f4087-ab17-480a-96e7-44f7cdc9d859
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494376036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2494376036
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2549451970
Short name T43
Test name
Test status
Simulation time 117769405 ps
CPU time 0.85 seconds
Started Jun 02 01:42:28 PM PDT 24
Finished Jun 02 01:42:30 PM PDT 24
Peak memory 213652 kb
Host smart-ea5fafbe-5a63-4519-ae5b-c461f807fc13
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549451970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2549451970
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.493548682
Short name T432
Test name
Test status
Simulation time 98100212 ps
CPU time 1.57 seconds
Started Jun 02 01:42:20 PM PDT 24
Finished Jun 02 01:42:22 PM PDT 24
Peak memory 198012 kb
Host smart-8f7268b7-f15e-48d9-994b-1e9b4cb0bfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493548682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.493548682
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2868965859
Short name T236
Test name
Test status
Simulation time 38577332 ps
CPU time 1.05 seconds
Started Jun 02 01:42:23 PM PDT 24
Finished Jun 02 01:42:24 PM PDT 24
Peak memory 196320 kb
Host smart-fc7c82a4-21f9-4480-a020-99495fc18dea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868965859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2868965859
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2263713520
Short name T621
Test name
Test status
Simulation time 1885308231 ps
CPU time 46.25 seconds
Started Jun 02 01:42:27 PM PDT 24
Finished Jun 02 01:43:14 PM PDT 24
Peak memory 197976 kb
Host smart-5a772c6e-5420-4d89-b03f-9bcf87bd446f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263713520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2263713520
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.4154419532
Short name T522
Test name
Test status
Simulation time 125807281346 ps
CPU time 584.67 seconds
Started Jun 02 01:42:28 PM PDT 24
Finished Jun 02 01:52:14 PM PDT 24
Peak memory 198244 kb
Host smart-950dc098-5032-4e0b-a486-5c53fc1f5246
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4154419532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.4154419532
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3182295554
Short name T450
Test name
Test status
Simulation time 131322611 ps
CPU time 0.57 seconds
Started Jun 02 01:43:39 PM PDT 24
Finished Jun 02 01:43:40 PM PDT 24
Peak memory 193832 kb
Host smart-a6609648-e377-4745-a50c-c09e15e1b81d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182295554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3182295554
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1647543992
Short name T350
Test name
Test status
Simulation time 48330789 ps
CPU time 0.78 seconds
Started Jun 02 01:43:40 PM PDT 24
Finished Jun 02 01:43:42 PM PDT 24
Peak memory 195420 kb
Host smart-abc0ccf1-177e-4ce3-9f9d-8c0c7e04e334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647543992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1647543992
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.83673848
Short name T193
Test name
Test status
Simulation time 967667132 ps
CPU time 12.77 seconds
Started Jun 02 01:43:39 PM PDT 24
Finished Jun 02 01:43:53 PM PDT 24
Peak memory 197996 kb
Host smart-9bc60196-b14f-4030-a48a-4b1356bffd38
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83673848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stress
.83673848
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.29135867
Short name T410
Test name
Test status
Simulation time 41415416 ps
CPU time 0.77 seconds
Started Jun 02 01:43:40 PM PDT 24
Finished Jun 02 01:43:42 PM PDT 24
Peak memory 194792 kb
Host smart-91a29120-782c-4f8e-b041-137ae9da5671
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29135867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.29135867
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.370350815
Short name T355
Test name
Test status
Simulation time 16857419 ps
CPU time 0.69 seconds
Started Jun 02 01:43:38 PM PDT 24
Finished Jun 02 01:43:40 PM PDT 24
Peak memory 194300 kb
Host smart-7d4a0e60-b295-4f4b-a4a9-8699e16448f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370350815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.370350815
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2434502933
Short name T419
Test name
Test status
Simulation time 71270640 ps
CPU time 2.9 seconds
Started Jun 02 01:43:43 PM PDT 24
Finished Jun 02 01:43:46 PM PDT 24
Peak memory 198056 kb
Host smart-71f27c7a-4193-450e-b381-dee3da3ac3fa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434502933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2434502933
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2766030458
Short name T47
Test name
Test status
Simulation time 94653894 ps
CPU time 3.03 seconds
Started Jun 02 01:43:40 PM PDT 24
Finished Jun 02 01:43:44 PM PDT 24
Peak memory 198048 kb
Host smart-e9f219ca-bf56-45b5-ba2d-6a1eb6c3b545
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766030458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2766030458
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.743593986
Short name T136
Test name
Test status
Simulation time 55488123 ps
CPU time 1.32 seconds
Started Jun 02 01:43:41 PM PDT 24
Finished Jun 02 01:43:43 PM PDT 24
Peak memory 198288 kb
Host smart-d158aba3-f080-4684-b2e1-61b2b6612e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743593986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.743593986
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2708138800
Short name T187
Test name
Test status
Simulation time 65175275 ps
CPU time 0.93 seconds
Started Jun 02 01:43:39 PM PDT 24
Finished Jun 02 01:43:41 PM PDT 24
Peak memory 196492 kb
Host smart-338951a1-7933-4082-9d11-8ff47c7d56d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708138800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2708138800
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1738835196
Short name T322
Test name
Test status
Simulation time 354556079 ps
CPU time 4.14 seconds
Started Jun 02 01:43:39 PM PDT 24
Finished Jun 02 01:43:44 PM PDT 24
Peak memory 197812 kb
Host smart-4a815475-e08b-4f83-b64e-02e57ccb42d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738835196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1738835196
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3337860419
Short name T484
Test name
Test status
Simulation time 58135052 ps
CPU time 0.72 seconds
Started Jun 02 01:43:37 PM PDT 24
Finished Jun 02 01:43:38 PM PDT 24
Peak memory 195116 kb
Host smart-30dd4e0b-183f-4d67-b48d-acf52b167263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337860419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3337860419
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2611605258
Short name T581
Test name
Test status
Simulation time 696849089 ps
CPU time 1.45 seconds
Started Jun 02 01:43:39 PM PDT 24
Finished Jun 02 01:43:41 PM PDT 24
Peak memory 196660 kb
Host smart-5511a198-8a1f-48ac-8938-366700626b90
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611605258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2611605258
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.4169363527
Short name T135
Test name
Test status
Simulation time 19309632694 ps
CPU time 71.94 seconds
Started Jun 02 01:43:37 PM PDT 24
Finished Jun 02 01:44:50 PM PDT 24
Peak memory 198196 kb
Host smart-044f5ed5-4338-4023-a261-47b83942a411
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169363527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.4169363527
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3470751874
Short name T481
Test name
Test status
Simulation time 21154527 ps
CPU time 0.57 seconds
Started Jun 02 01:43:43 PM PDT 24
Finished Jun 02 01:43:44 PM PDT 24
Peak memory 194576 kb
Host smart-42472cfc-f7d3-484d-8803-72d60ee9feb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470751874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3470751874
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2461699754
Short name T333
Test name
Test status
Simulation time 18337965 ps
CPU time 0.67 seconds
Started Jun 02 01:43:39 PM PDT 24
Finished Jun 02 01:43:40 PM PDT 24
Peak memory 194264 kb
Host smart-baf308ff-87a0-487e-9d4a-372176b05de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461699754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2461699754
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2766358339
Short name T405
Test name
Test status
Simulation time 4847437574 ps
CPU time 23.68 seconds
Started Jun 02 01:43:41 PM PDT 24
Finished Jun 02 01:44:06 PM PDT 24
Peak memory 196976 kb
Host smart-1013ae70-15c5-42ab-a1c4-0f60b52bfb85
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766358339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2766358339
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1304541235
Short name T252
Test name
Test status
Simulation time 99284873 ps
CPU time 0.66 seconds
Started Jun 02 01:43:46 PM PDT 24
Finished Jun 02 01:43:48 PM PDT 24
Peak memory 195324 kb
Host smart-216c604e-eb01-4310-8fdc-a52e48ecbde2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304541235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1304541235
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2837432023
Short name T126
Test name
Test status
Simulation time 21729204 ps
CPU time 0.67 seconds
Started Jun 02 01:43:39 PM PDT 24
Finished Jun 02 01:43:40 PM PDT 24
Peak memory 194208 kb
Host smart-c1cd2dee-2f04-48dd-821d-8bbe093bdacd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837432023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2837432023
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2141044499
Short name T325
Test name
Test status
Simulation time 124542996 ps
CPU time 1.72 seconds
Started Jun 02 01:43:42 PM PDT 24
Finished Jun 02 01:43:44 PM PDT 24
Peak memory 196440 kb
Host smart-d5d2aed6-f8ff-47fc-844f-7eb4b5eb1f30
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141044499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2141044499
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.225352204
Short name T241
Test name
Test status
Simulation time 1350946896 ps
CPU time 1.63 seconds
Started Jun 02 01:43:41 PM PDT 24
Finished Jun 02 01:43:43 PM PDT 24
Peak memory 196080 kb
Host smart-24887d65-258e-4a6c-846d-7238c67fdf4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225352204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
225352204
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3024825823
Short name T566
Test name
Test status
Simulation time 22351786 ps
CPU time 0.87 seconds
Started Jun 02 01:43:40 PM PDT 24
Finished Jun 02 01:43:41 PM PDT 24
Peak memory 195924 kb
Host smart-c74120d0-948f-446f-a8c5-0e02b194aaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024825823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3024825823
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3450424146
Short name T374
Test name
Test status
Simulation time 62689516 ps
CPU time 0.74 seconds
Started Jun 02 01:43:40 PM PDT 24
Finished Jun 02 01:43:42 PM PDT 24
Peak memory 196044 kb
Host smart-823399ea-d699-484f-ae8d-813cff04ee3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450424146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3450424146
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2134305575
Short name T291
Test name
Test status
Simulation time 1178230690 ps
CPU time 3.54 seconds
Started Jun 02 01:43:42 PM PDT 24
Finished Jun 02 01:43:46 PM PDT 24
Peak memory 197948 kb
Host smart-22ddbf56-2956-4ba4-874f-02813418c3bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134305575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2134305575
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.942758480
Short name T373
Test name
Test status
Simulation time 143864406 ps
CPU time 1.08 seconds
Started Jun 02 01:43:42 PM PDT 24
Finished Jun 02 01:43:43 PM PDT 24
Peak memory 195756 kb
Host smart-5e8c0641-bb63-43ee-9812-df5f8d8abdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942758480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.942758480
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.1726349167
Short name T595
Test name
Test status
Simulation time 286920067 ps
CPU time 1.21 seconds
Started Jun 02 01:43:42 PM PDT 24
Finished Jun 02 01:43:44 PM PDT 24
Peak memory 196820 kb
Host smart-ccb0aabb-08da-4a1c-903e-7734d5fc3bfc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726349167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1726349167
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1786368780
Short name T469
Test name
Test status
Simulation time 13529271764 ps
CPU time 144.47 seconds
Started Jun 02 01:43:44 PM PDT 24
Finished Jun 02 01:46:09 PM PDT 24
Peak memory 198116 kb
Host smart-ee3485bc-e058-4841-aca9-5c16e85a9c85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786368780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1786368780
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3991139108
Short name T386
Test name
Test status
Simulation time 43326375 ps
CPU time 0.59 seconds
Started Jun 02 01:43:45 PM PDT 24
Finished Jun 02 01:43:46 PM PDT 24
Peak memory 194552 kb
Host smart-ac67d732-4c44-4182-b5cd-4bdfb4ba3f46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991139108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3991139108
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.568912745
Short name T684
Test name
Test status
Simulation time 171259113 ps
CPU time 0.96 seconds
Started Jun 02 01:43:47 PM PDT 24
Finished Jun 02 01:43:48 PM PDT 24
Peak memory 195700 kb
Host smart-1cbc818a-62ba-438d-8e52-9721d5be00e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568912745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.568912745
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2470866459
Short name T273
Test name
Test status
Simulation time 1584941346 ps
CPU time 26.86 seconds
Started Jun 02 01:43:45 PM PDT 24
Finished Jun 02 01:44:12 PM PDT 24
Peak memory 196920 kb
Host smart-dacce57b-afc1-4b68-8c49-126f3ab1da9d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470866459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2470866459
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1479028498
Short name T266
Test name
Test status
Simulation time 938045957 ps
CPU time 0.93 seconds
Started Jun 02 01:43:43 PM PDT 24
Finished Jun 02 01:43:44 PM PDT 24
Peak memory 197096 kb
Host smart-3204a866-bb36-44a7-a8c4-268829f79085
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479028498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1479028498
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3944944444
Short name T349
Test name
Test status
Simulation time 189892923 ps
CPU time 1.41 seconds
Started Jun 02 01:43:43 PM PDT 24
Finished Jun 02 01:43:45 PM PDT 24
Peak memory 198304 kb
Host smart-50cef3c0-6164-4417-bc27-e3906d6285ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944944444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3944944444
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2880334135
Short name T330
Test name
Test status
Simulation time 162464560 ps
CPU time 3.05 seconds
Started Jun 02 01:43:43 PM PDT 24
Finished Jun 02 01:43:47 PM PDT 24
Peak memory 198024 kb
Host smart-13d7056a-acfc-4019-9d8b-363312ed0d13
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880334135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2880334135
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1579383745
Short name T675
Test name
Test status
Simulation time 106720387 ps
CPU time 2.06 seconds
Started Jun 02 01:43:44 PM PDT 24
Finished Jun 02 01:43:46 PM PDT 24
Peak memory 196104 kb
Host smart-e2b79763-0c3d-49a1-8af8-adffddc6aeb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579383745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1579383745
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3042198230
Short name T161
Test name
Test status
Simulation time 46077188 ps
CPU time 1.04 seconds
Started Jun 02 01:43:45 PM PDT 24
Finished Jun 02 01:43:46 PM PDT 24
Peak memory 196632 kb
Host smart-d2e2a24c-06e8-4909-a3eb-2cc8b06085ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042198230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3042198230
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.924138898
Short name T224
Test name
Test status
Simulation time 36900068 ps
CPU time 0.85 seconds
Started Jun 02 01:43:47 PM PDT 24
Finished Jun 02 01:43:48 PM PDT 24
Peak memory 196496 kb
Host smart-2fc0a6fa-840a-4535-92dd-49021814cbf5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924138898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.924138898
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2642398893
Short name T51
Test name
Test status
Simulation time 205619427 ps
CPU time 2.02 seconds
Started Jun 02 01:43:43 PM PDT 24
Finished Jun 02 01:43:46 PM PDT 24
Peak memory 198032 kb
Host smart-045f3770-b7f1-4e0e-a7c8-2b321dd0dcde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642398893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2642398893
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.592316646
Short name T142
Test name
Test status
Simulation time 109777659 ps
CPU time 0.97 seconds
Started Jun 02 01:43:43 PM PDT 24
Finished Jun 02 01:43:45 PM PDT 24
Peak memory 196304 kb
Host smart-f4c465c0-e5ce-4b46-a818-e981a19d78e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592316646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.592316646
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.703172149
Short name T179
Test name
Test status
Simulation time 51042444 ps
CPU time 0.95 seconds
Started Jun 02 01:43:43 PM PDT 24
Finished Jun 02 01:43:44 PM PDT 24
Peak memory 195504 kb
Host smart-4fb47144-45bb-44ff-8504-9fdbdc2452b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703172149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.703172149
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1500999643
Short name T695
Test name
Test status
Simulation time 2408199431 ps
CPU time 60.17 seconds
Started Jun 02 01:43:47 PM PDT 24
Finished Jun 02 01:44:48 PM PDT 24
Peak memory 198124 kb
Host smart-a19037e4-f8e2-4847-b6ae-ef8c8b0a6168
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500999643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1500999643
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1260001514
Short name T464
Test name
Test status
Simulation time 12187388 ps
CPU time 0.58 seconds
Started Jun 02 01:43:43 PM PDT 24
Finished Jun 02 01:43:44 PM PDT 24
Peak memory 193888 kb
Host smart-61ac181a-f3e2-4729-92ea-54f316c2ffa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260001514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1260001514
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2459463381
Short name T217
Test name
Test status
Simulation time 43980420 ps
CPU time 0.86 seconds
Started Jun 02 01:43:46 PM PDT 24
Finished Jun 02 01:43:48 PM PDT 24
Peak memory 196328 kb
Host smart-f573c245-c541-48ac-92a7-476633b76041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459463381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2459463381
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3355139330
Short name T379
Test name
Test status
Simulation time 1710662706 ps
CPU time 24.76 seconds
Started Jun 02 01:43:46 PM PDT 24
Finished Jun 02 01:44:11 PM PDT 24
Peak memory 197992 kb
Host smart-b6c784dc-6f0f-453f-a9b0-f4b90079bfca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355139330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3355139330
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3254815314
Short name T560
Test name
Test status
Simulation time 314495001 ps
CPU time 1.04 seconds
Started Jun 02 01:43:44 PM PDT 24
Finished Jun 02 01:43:46 PM PDT 24
Peak memory 196684 kb
Host smart-96071da3-d039-4d8f-8186-4981a2bfece4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254815314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3254815314
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3422302023
Short name T50
Test name
Test status
Simulation time 97886188 ps
CPU time 1.37 seconds
Started Jun 02 01:43:42 PM PDT 24
Finished Jun 02 01:43:44 PM PDT 24
Peak memory 196916 kb
Host smart-f9c33d4c-17a0-4cd2-a6d6-9a784090596b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422302023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3422302023
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.817386930
Short name T159
Test name
Test status
Simulation time 40199453 ps
CPU time 0.99 seconds
Started Jun 02 01:43:42 PM PDT 24
Finished Jun 02 01:43:44 PM PDT 24
Peak memory 196192 kb
Host smart-c7be2801-9f84-4cb8-941d-cc0f1b173742
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817386930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.817386930
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3542946580
Short name T613
Test name
Test status
Simulation time 185458651 ps
CPU time 3.22 seconds
Started Jun 02 01:43:44 PM PDT 24
Finished Jun 02 01:43:48 PM PDT 24
Peak memory 198032 kb
Host smart-5f7ed253-b60f-48cd-be97-dffc8b0c063f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542946580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3542946580
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2057737463
Short name T700
Test name
Test status
Simulation time 209030018 ps
CPU time 1.29 seconds
Started Jun 02 01:43:46 PM PDT 24
Finished Jun 02 01:43:48 PM PDT 24
Peak memory 197984 kb
Host smart-87362054-8d3f-4662-bfb7-d9a5ebd945da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057737463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2057737463
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1186510157
Short name T138
Test name
Test status
Simulation time 30883227 ps
CPU time 0.85 seconds
Started Jun 02 01:43:43 PM PDT 24
Finished Jun 02 01:43:44 PM PDT 24
Peak memory 196688 kb
Host smart-423083c7-8a7f-48bc-9809-2cab8960125b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186510157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1186510157
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3842401573
Short name T137
Test name
Test status
Simulation time 43516481 ps
CPU time 2.08 seconds
Started Jun 02 01:43:46 PM PDT 24
Finished Jun 02 01:43:49 PM PDT 24
Peak memory 198048 kb
Host smart-b5b05eb6-e02b-4857-8e5c-0bf19beb8250
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842401573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3842401573
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3930172434
Short name T359
Test name
Test status
Simulation time 32891133 ps
CPU time 0.86 seconds
Started Jun 02 01:43:46 PM PDT 24
Finished Jun 02 01:43:48 PM PDT 24
Peak memory 196444 kb
Host smart-c2c5605e-d831-4493-bff8-2ab09cece7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930172434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3930172434
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2422463293
Short name T485
Test name
Test status
Simulation time 36243289 ps
CPU time 0.95 seconds
Started Jun 02 01:43:46 PM PDT 24
Finished Jun 02 01:43:48 PM PDT 24
Peak memory 196512 kb
Host smart-f1de8f4f-a2e1-45c9-b3ec-f6c656569fb3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422463293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2422463293
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.2723954908
Short name T21
Test name
Test status
Simulation time 67352408213 ps
CPU time 174.52 seconds
Started Jun 02 01:43:44 PM PDT 24
Finished Jun 02 01:46:39 PM PDT 24
Peak memory 198192 kb
Host smart-fe617064-41a9-4ceb-afc1-c74f62da06e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723954908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.2723954908
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2716181434
Short name T335
Test name
Test status
Simulation time 11999764 ps
CPU time 0.61 seconds
Started Jun 02 01:43:50 PM PDT 24
Finished Jun 02 01:43:51 PM PDT 24
Peak memory 194540 kb
Host smart-3a003610-6e46-4584-904f-ed59a6d1644e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716181434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2716181434
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2937032630
Short name T243
Test name
Test status
Simulation time 110567748 ps
CPU time 0.76 seconds
Started Jun 02 01:43:53 PM PDT 24
Finished Jun 02 01:43:54 PM PDT 24
Peak memory 196048 kb
Host smart-59b218aa-f478-4afe-b524-41b48d5a8ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937032630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2937032630
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2561242229
Short name T134
Test name
Test status
Simulation time 114938759 ps
CPU time 3.38 seconds
Started Jun 02 01:43:49 PM PDT 24
Finished Jun 02 01:43:53 PM PDT 24
Peak memory 195480 kb
Host smart-bf09d136-46ef-43c9-838e-d9140782c757
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561242229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2561242229
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1788089962
Short name T186
Test name
Test status
Simulation time 111677762 ps
CPU time 1.01 seconds
Started Jun 02 01:43:49 PM PDT 24
Finished Jun 02 01:43:51 PM PDT 24
Peak memory 198000 kb
Host smart-0019b019-d2ed-486a-8fec-70a414504373
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788089962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1788089962
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3114333916
Short name T713
Test name
Test status
Simulation time 44797649 ps
CPU time 0.97 seconds
Started Jun 02 01:43:49 PM PDT 24
Finished Jun 02 01:43:51 PM PDT 24
Peak memory 196668 kb
Host smart-96c77bd3-d0cc-40aa-84aa-be5a6185392f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114333916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3114333916
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1787976387
Short name T389
Test name
Test status
Simulation time 77384901 ps
CPU time 3.09 seconds
Started Jun 02 01:43:51 PM PDT 24
Finished Jun 02 01:43:55 PM PDT 24
Peak memory 198056 kb
Host smart-cbe133c0-6b14-4b07-8776-5f350f6413ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787976387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1787976387
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2354648852
Short name T425
Test name
Test status
Simulation time 57088490 ps
CPU time 1.07 seconds
Started Jun 02 01:43:50 PM PDT 24
Finished Jun 02 01:43:52 PM PDT 24
Peak memory 195684 kb
Host smart-d6d6c77d-f871-4a95-aed8-6086ba657c4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354648852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2354648852
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2099186344
Short name T166
Test name
Test status
Simulation time 76967243 ps
CPU time 1.28 seconds
Started Jun 02 01:43:45 PM PDT 24
Finished Jun 02 01:43:46 PM PDT 24
Peak memory 197044 kb
Host smart-b92dc7a7-0f1a-4115-b719-2eb3aab06316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099186344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2099186344
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2644163241
Short name T578
Test name
Test status
Simulation time 34557321 ps
CPU time 0.8 seconds
Started Jun 02 01:43:49 PM PDT 24
Finished Jun 02 01:43:50 PM PDT 24
Peak memory 195528 kb
Host smart-892aad35-0f1a-4704-ade1-574a5ec43b8e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644163241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2644163241
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1451771422
Short name T303
Test name
Test status
Simulation time 72628179 ps
CPU time 3.47 seconds
Started Jun 02 01:43:49 PM PDT 24
Finished Jun 02 01:43:53 PM PDT 24
Peak memory 198020 kb
Host smart-8fcea13e-a643-4276-bd24-46a4aea1b88b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451771422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1451771422
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2817182407
Short name T248
Test name
Test status
Simulation time 74293582 ps
CPU time 1.39 seconds
Started Jun 02 01:43:46 PM PDT 24
Finished Jun 02 01:43:48 PM PDT 24
Peak memory 196836 kb
Host smart-7d961e36-5ff4-4061-9f9b-72b1f26a25c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817182407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2817182407
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3437191873
Short name T180
Test name
Test status
Simulation time 229152015 ps
CPU time 1.08 seconds
Started Jun 02 01:43:46 PM PDT 24
Finished Jun 02 01:43:48 PM PDT 24
Peak memory 195784 kb
Host smart-f352cc7a-a10c-42eb-bd8f-87e97a7786c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437191873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3437191873
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3099068996
Short name T658
Test name
Test status
Simulation time 23154868052 ps
CPU time 135.39 seconds
Started Jun 02 01:43:49 PM PDT 24
Finished Jun 02 01:46:05 PM PDT 24
Peak memory 198180 kb
Host smart-b026ecba-5f16-4a9a-bf27-b0f0e3a581f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099068996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3099068996
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2296406158
Short name T598
Test name
Test status
Simulation time 47552575 ps
CPU time 0.58 seconds
Started Jun 02 01:43:51 PM PDT 24
Finished Jun 02 01:43:52 PM PDT 24
Peak memory 194460 kb
Host smart-762a2843-e96e-4777-979e-2dd2281d78ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296406158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2296406158
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2587541014
Short name T468
Test name
Test status
Simulation time 51809489 ps
CPU time 0.9 seconds
Started Jun 02 01:43:51 PM PDT 24
Finished Jun 02 01:43:52 PM PDT 24
Peak memory 196616 kb
Host smart-9bd75a94-9b03-4654-b1fb-1e928618e2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587541014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2587541014
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1912630226
Short name T370
Test name
Test status
Simulation time 480684992 ps
CPU time 5.22 seconds
Started Jun 02 01:43:47 PM PDT 24
Finished Jun 02 01:43:53 PM PDT 24
Peak memory 196636 kb
Host smart-bc380ade-f8eb-45b4-8257-2ad3283b1396
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912630226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1912630226
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2172949194
Short name T313
Test name
Test status
Simulation time 391317518 ps
CPU time 0.97 seconds
Started Jun 02 01:43:51 PM PDT 24
Finished Jun 02 01:43:53 PM PDT 24
Peak memory 197704 kb
Host smart-1932ab06-4215-4b2b-9cd4-d6ce5b056eff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172949194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2172949194
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1213294070
Short name T636
Test name
Test status
Simulation time 131809122 ps
CPU time 0.92 seconds
Started Jun 02 01:43:49 PM PDT 24
Finished Jun 02 01:43:51 PM PDT 24
Peak memory 196304 kb
Host smart-fef74e06-98bf-4753-8fa5-5ec8683d6a74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213294070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1213294070
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2625021159
Short name T295
Test name
Test status
Simulation time 97932722 ps
CPU time 2.13 seconds
Started Jun 02 01:43:51 PM PDT 24
Finished Jun 02 01:43:54 PM PDT 24
Peak memory 198044 kb
Host smart-16cec6b1-c0e9-47eb-a60b-571418d31cd1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625021159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2625021159
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3759986669
Short name T174
Test name
Test status
Simulation time 90719801 ps
CPU time 0.97 seconds
Started Jun 02 01:43:52 PM PDT 24
Finished Jun 02 01:43:53 PM PDT 24
Peak memory 195432 kb
Host smart-8f14f98e-9952-41f5-9937-dce9d733de23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759986669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3759986669
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1659500181
Short name T114
Test name
Test status
Simulation time 28244407 ps
CPU time 0.76 seconds
Started Jun 02 01:43:50 PM PDT 24
Finished Jun 02 01:43:51 PM PDT 24
Peak memory 195480 kb
Host smart-150fd99b-e426-4d37-95e3-4803b82930c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659500181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1659500181
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1596347487
Short name T494
Test name
Test status
Simulation time 43950401 ps
CPU time 1.06 seconds
Started Jun 02 01:43:47 PM PDT 24
Finished Jun 02 01:43:49 PM PDT 24
Peak memory 195980 kb
Host smart-7f62bdcd-7a98-4209-8c71-878b0bc187f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596347487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1596347487
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.789316830
Short name T440
Test name
Test status
Simulation time 412532916 ps
CPU time 4.69 seconds
Started Jun 02 01:43:50 PM PDT 24
Finished Jun 02 01:43:55 PM PDT 24
Peak memory 197920 kb
Host smart-cc263040-b49f-4b3b-9315-960b9fd70eb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789316830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.789316830
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.4090036807
Short name T422
Test name
Test status
Simulation time 415483878 ps
CPU time 1.47 seconds
Started Jun 02 01:43:48 PM PDT 24
Finished Jun 02 01:43:51 PM PDT 24
Peak memory 197968 kb
Host smart-1ada985d-6c49-4f87-8679-246d0ede8655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090036807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.4090036807
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1084099916
Short name T269
Test name
Test status
Simulation time 88430653 ps
CPU time 0.96 seconds
Started Jun 02 01:43:49 PM PDT 24
Finished Jun 02 01:43:51 PM PDT 24
Peak memory 197160 kb
Host smart-64e9abf7-ebe1-4d22-9a5a-a5e4a6d2c161
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084099916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1084099916
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3886452418
Short name T274
Test name
Test status
Simulation time 13973186935 ps
CPU time 121.29 seconds
Started Jun 02 01:43:49 PM PDT 24
Finished Jun 02 01:45:51 PM PDT 24
Peak memory 198128 kb
Host smart-f654fdc2-bf87-4c80-8df3-64dfff7e1fc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886452418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3886452418
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3063098740
Short name T638
Test name
Test status
Simulation time 36777288 ps
CPU time 0.55 seconds
Started Jun 02 01:43:49 PM PDT 24
Finished Jun 02 01:43:50 PM PDT 24
Peak memory 193872 kb
Host smart-4fbb5c63-f4bb-4498-9392-4f08dbd2831d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063098740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3063098740
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.379273973
Short name T515
Test name
Test status
Simulation time 115110706 ps
CPU time 0.8 seconds
Started Jun 02 01:43:50 PM PDT 24
Finished Jun 02 01:43:51 PM PDT 24
Peak memory 195200 kb
Host smart-26bb38b5-9e07-454d-ac13-3f6661597f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379273973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.379273973
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.341266551
Short name T263
Test name
Test status
Simulation time 741491333 ps
CPU time 6.12 seconds
Started Jun 02 01:43:55 PM PDT 24
Finished Jun 02 01:44:02 PM PDT 24
Peak memory 197972 kb
Host smart-8ad6c5d8-9010-4c03-adeb-5882ba7aa083
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341266551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.341266551
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.859421066
Short name T615
Test name
Test status
Simulation time 289450978 ps
CPU time 1.05 seconds
Started Jun 02 01:43:52 PM PDT 24
Finished Jun 02 01:43:53 PM PDT 24
Peak memory 197896 kb
Host smart-e8cdd227-488c-4533-a4d4-c956e6eec378
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859421066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.859421066
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3336215283
Short name T641
Test name
Test status
Simulation time 82190554 ps
CPU time 1.06 seconds
Started Jun 02 01:43:51 PM PDT 24
Finished Jun 02 01:43:53 PM PDT 24
Peak memory 196684 kb
Host smart-743629ea-8bc8-47dd-8102-752e10be4d00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336215283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3336215283
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3850724100
Short name T258
Test name
Test status
Simulation time 103675202 ps
CPU time 1.02 seconds
Started Jun 02 01:43:50 PM PDT 24
Finished Jun 02 01:43:52 PM PDT 24
Peak memory 197072 kb
Host smart-b40bce7a-5820-4139-a5b9-aab11f0012cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850724100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3850724100
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.24980864
Short name T332
Test name
Test status
Simulation time 56627722 ps
CPU time 1.78 seconds
Started Jun 02 01:43:50 PM PDT 24
Finished Jun 02 01:43:53 PM PDT 24
Peak memory 196248 kb
Host smart-b4d592c6-5fda-448c-ab3a-02004e4aacaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24980864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.24980864
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3069302139
Short name T628
Test name
Test status
Simulation time 34990556 ps
CPU time 0.71 seconds
Started Jun 02 01:43:51 PM PDT 24
Finished Jun 02 01:43:52 PM PDT 24
Peak memory 195452 kb
Host smart-0b9943cf-3ee9-4857-b256-b860aaf9606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069302139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3069302139
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3004710035
Short name T191
Test name
Test status
Simulation time 102550433 ps
CPU time 0.98 seconds
Started Jun 02 01:43:48 PM PDT 24
Finished Jun 02 01:43:50 PM PDT 24
Peak memory 195920 kb
Host smart-672be33e-4611-4c4d-b7f5-08fa7c0bbcd3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004710035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3004710035
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3592406965
Short name T627
Test name
Test status
Simulation time 292347730 ps
CPU time 5.35 seconds
Started Jun 02 01:43:49 PM PDT 24
Finished Jun 02 01:43:55 PM PDT 24
Peak memory 197960 kb
Host smart-061e5b31-8a5d-4b3f-abaf-c17012056f31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592406965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3592406965
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.998760710
Short name T537
Test name
Test status
Simulation time 237032615 ps
CPU time 1.16 seconds
Started Jun 02 01:43:51 PM PDT 24
Finished Jun 02 01:43:52 PM PDT 24
Peak memory 195248 kb
Host smart-6b6944fa-4262-4260-a04e-344be2e53b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998760710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.998760710
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2393564008
Short name T668
Test name
Test status
Simulation time 44340416 ps
CPU time 0.92 seconds
Started Jun 02 01:43:50 PM PDT 24
Finished Jun 02 01:43:51 PM PDT 24
Peak memory 196308 kb
Host smart-c310389d-d792-45d4-a728-b2059bf19e21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393564008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2393564008
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2526894012
Short name T539
Test name
Test status
Simulation time 10915422250 ps
CPU time 77.59 seconds
Started Jun 02 01:43:51 PM PDT 24
Finished Jun 02 01:45:09 PM PDT 24
Peak memory 198124 kb
Host smart-aa8592af-1007-42ab-a9c1-e88d079a31a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526894012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2526894012
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.1539194718
Short name T54
Test name
Test status
Simulation time 334816634169 ps
CPU time 967.93 seconds
Started Jun 02 01:43:49 PM PDT 24
Finished Jun 02 01:59:58 PM PDT 24
Peak memory 198200 kb
Host smart-79f82d1b-1e17-4ecc-b49b-4a60c1a46309
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1539194718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.1539194718
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2376019100
Short name T394
Test name
Test status
Simulation time 12751838 ps
CPU time 0.59 seconds
Started Jun 02 01:43:53 PM PDT 24
Finished Jun 02 01:43:54 PM PDT 24
Peak memory 194528 kb
Host smart-218f3352-4cd3-4cbd-a54c-c44f3d0d8578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376019100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2376019100
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.4139085496
Short name T643
Test name
Test status
Simulation time 40944715 ps
CPU time 0.93 seconds
Started Jun 02 01:43:55 PM PDT 24
Finished Jun 02 01:43:56 PM PDT 24
Peak memory 196376 kb
Host smart-58a5b9c2-2bf4-415d-97ca-d124e323afdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139085496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.4139085496
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3888591221
Short name T24
Test name
Test status
Simulation time 598482291 ps
CPU time 24.45 seconds
Started Jun 02 01:43:57 PM PDT 24
Finished Jun 02 01:44:21 PM PDT 24
Peak memory 197920 kb
Host smart-16414b8f-f245-4cca-bbcb-e77d6b15bfb9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888591221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3888591221
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2327401840
Short name T206
Test name
Test status
Simulation time 138029423 ps
CPU time 0.67 seconds
Started Jun 02 01:43:55 PM PDT 24
Finished Jun 02 01:43:56 PM PDT 24
Peak memory 194660 kb
Host smart-273a8d45-9e2a-4f8f-901e-4017cbd6c46a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327401840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2327401840
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.959803417
Short name T117
Test name
Test status
Simulation time 22762987 ps
CPU time 0.73 seconds
Started Jun 02 01:43:58 PM PDT 24
Finished Jun 02 01:43:59 PM PDT 24
Peak memory 194280 kb
Host smart-4e648e26-02b9-4df8-a2e5-7663fc951079
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959803417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.959803417
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.359868128
Short name T454
Test name
Test status
Simulation time 63609930 ps
CPU time 2.39 seconds
Started Jun 02 01:43:56 PM PDT 24
Finished Jun 02 01:43:59 PM PDT 24
Peak memory 198084 kb
Host smart-7479c995-ce86-46e2-a87e-60ea61a79f73
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359868128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.359868128
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2924557711
Short name T567
Test name
Test status
Simulation time 122467473 ps
CPU time 2.52 seconds
Started Jun 02 01:43:56 PM PDT 24
Finished Jun 02 01:43:59 PM PDT 24
Peak memory 197120 kb
Host smart-8f10a5bd-f31d-4c53-954d-a698d6ccffb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924557711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2924557711
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1889352687
Short name T272
Test name
Test status
Simulation time 190044032 ps
CPU time 0.98 seconds
Started Jun 02 01:43:58 PM PDT 24
Finished Jun 02 01:43:59 PM PDT 24
Peak memory 195864 kb
Host smart-ce0a5d81-25b9-4ea8-819a-6128b7234f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889352687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1889352687
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.633597769
Short name T239
Test name
Test status
Simulation time 20386116 ps
CPU time 0.7 seconds
Started Jun 02 01:43:53 PM PDT 24
Finished Jun 02 01:43:54 PM PDT 24
Peak memory 195384 kb
Host smart-f0026990-8ef8-4200-bb6e-01f22c8f5b49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633597769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.633597769
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3994556035
Short name T9
Test name
Test status
Simulation time 2527462093 ps
CPU time 5.4 seconds
Started Jun 02 01:43:56 PM PDT 24
Finished Jun 02 01:44:02 PM PDT 24
Peak memory 198088 kb
Host smart-9902df77-92f1-4db2-ab7d-09f2fd7bdde3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994556035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3994556035
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.752870423
Short name T218
Test name
Test status
Simulation time 94023408 ps
CPU time 1.52 seconds
Started Jun 02 01:43:54 PM PDT 24
Finished Jun 02 01:43:56 PM PDT 24
Peak memory 196744 kb
Host smart-3fe3b7d6-5834-44b5-8745-6151acfb47dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752870423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.752870423
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1486445922
Short name T320
Test name
Test status
Simulation time 109333127 ps
CPU time 1.1 seconds
Started Jun 02 01:43:56 PM PDT 24
Finished Jun 02 01:43:58 PM PDT 24
Peak memory 196544 kb
Host smart-96b5c3a8-228f-46ef-b398-0d358945f30c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486445922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1486445922
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1029039375
Short name T242
Test name
Test status
Simulation time 22187812665 ps
CPU time 67.35 seconds
Started Jun 02 01:43:56 PM PDT 24
Finished Jun 02 01:45:04 PM PDT 24
Peak memory 198232 kb
Host smart-1bba8648-aa15-4830-b523-3ab0f5d33373
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029039375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1029039375
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2592441989
Short name T645
Test name
Test status
Simulation time 30358230 ps
CPU time 0.6 seconds
Started Jun 02 01:44:01 PM PDT 24
Finished Jun 02 01:44:02 PM PDT 24
Peak memory 193840 kb
Host smart-dc6576da-6cfd-4bdf-91e8-c8c2ea7c6677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592441989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2592441989
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.305649228
Short name T115
Test name
Test status
Simulation time 33303648 ps
CPU time 0.61 seconds
Started Jun 02 01:43:54 PM PDT 24
Finished Jun 02 01:43:55 PM PDT 24
Peak memory 194796 kb
Host smart-5d9a6eb3-b569-412d-b191-d317b763d239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305649228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.305649228
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1905577093
Short name T275
Test name
Test status
Simulation time 551335631 ps
CPU time 16.53 seconds
Started Jun 02 01:43:58 PM PDT 24
Finished Jun 02 01:44:15 PM PDT 24
Peak memory 197952 kb
Host smart-e243be7c-8452-4ea8-a572-a693f08bba0c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905577093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1905577093
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.4178790429
Short name T10
Test name
Test status
Simulation time 231043501 ps
CPU time 0.85 seconds
Started Jun 02 01:43:55 PM PDT 24
Finished Jun 02 01:43:56 PM PDT 24
Peak memory 195956 kb
Host smart-4afdbbdc-1b7f-408c-bcab-90b597026423
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178790429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.4178790429
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2065889442
Short name T400
Test name
Test status
Simulation time 105163062 ps
CPU time 1.11 seconds
Started Jun 02 01:43:56 PM PDT 24
Finished Jun 02 01:43:57 PM PDT 24
Peak memory 195760 kb
Host smart-0c77e022-63af-4ed1-bbb6-df217b1c78f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065889442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2065889442
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3271350337
Short name T223
Test name
Test status
Simulation time 185180696 ps
CPU time 1.49 seconds
Started Jun 02 01:43:56 PM PDT 24
Finished Jun 02 01:43:58 PM PDT 24
Peak memory 196368 kb
Host smart-2264f4e0-e64f-419e-a2d6-2789050763c2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271350337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3271350337
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3437165991
Short name T268
Test name
Test status
Simulation time 355619750 ps
CPU time 1.98 seconds
Started Jun 02 01:43:55 PM PDT 24
Finished Jun 02 01:43:57 PM PDT 24
Peak memory 196012 kb
Host smart-dec2ebc0-3ec2-427c-92b5-830e330645ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437165991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3437165991
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3241745760
Short name T434
Test name
Test status
Simulation time 100799815 ps
CPU time 0.93 seconds
Started Jun 02 01:43:55 PM PDT 24
Finished Jun 02 01:43:56 PM PDT 24
Peak memory 196524 kb
Host smart-8179f319-e882-4af6-809f-cb7dafa7bb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241745760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3241745760
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.4213591300
Short name T497
Test name
Test status
Simulation time 56982534 ps
CPU time 0.84 seconds
Started Jun 02 01:43:54 PM PDT 24
Finished Jun 02 01:43:55 PM PDT 24
Peak memory 195544 kb
Host smart-2e450b8d-40fa-4245-9880-9261c8baaa93
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213591300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.4213591300
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3937376212
Short name T689
Test name
Test status
Simulation time 59334176 ps
CPU time 2.5 seconds
Started Jun 02 01:43:54 PM PDT 24
Finished Jun 02 01:43:56 PM PDT 24
Peak memory 197848 kb
Host smart-e42dbb9c-d21f-4db5-bc7b-48e3c45002ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937376212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3937376212
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3487860869
Short name T716
Test name
Test status
Simulation time 163564204 ps
CPU time 0.83 seconds
Started Jun 02 01:43:54 PM PDT 24
Finished Jun 02 01:43:55 PM PDT 24
Peak memory 195400 kb
Host smart-a73858b0-6448-4dc9-9ad7-38d0943417df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487860869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3487860869
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3738020088
Short name T513
Test name
Test status
Simulation time 415689889 ps
CPU time 1.22 seconds
Started Jun 02 01:43:57 PM PDT 24
Finished Jun 02 01:43:59 PM PDT 24
Peak memory 197952 kb
Host smart-71c517d6-cbd2-46a5-aa30-3c04ee65ab08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738020088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3738020088
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.114354548
Short name T445
Test name
Test status
Simulation time 4163411602 ps
CPU time 59.47 seconds
Started Jun 02 01:43:55 PM PDT 24
Finished Jun 02 01:44:55 PM PDT 24
Peak memory 198192 kb
Host smart-e963e108-719e-4e72-b76c-058ed3600e15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114354548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.114354548
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2920936998
Short name T505
Test name
Test status
Simulation time 32182135 ps
CPU time 0.58 seconds
Started Jun 02 01:44:00 PM PDT 24
Finished Jun 02 01:44:01 PM PDT 24
Peak memory 194032 kb
Host smart-c3e776ce-3e97-483b-932c-c76e069f32cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920936998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2920936998
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.664470562
Short name T644
Test name
Test status
Simulation time 86967852 ps
CPU time 0.86 seconds
Started Jun 02 01:44:01 PM PDT 24
Finished Jun 02 01:44:03 PM PDT 24
Peak memory 196184 kb
Host smart-f59617f1-c206-405a-b164-01e451fcdbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664470562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.664470562
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1590567652
Short name T506
Test name
Test status
Simulation time 697761908 ps
CPU time 16.31 seconds
Started Jun 02 01:44:02 PM PDT 24
Finished Jun 02 01:44:19 PM PDT 24
Peak memory 197992 kb
Host smart-d095e369-6b8b-4183-a3ed-d3e5326bfd66
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590567652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1590567652
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1397147258
Short name T446
Test name
Test status
Simulation time 60688096 ps
CPU time 0.91 seconds
Started Jun 02 01:44:02 PM PDT 24
Finished Jun 02 01:44:04 PM PDT 24
Peak memory 196080 kb
Host smart-628dbc61-ea59-4b05-88bd-a9ba521abe7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397147258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1397147258
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3185825937
Short name T496
Test name
Test status
Simulation time 87233069 ps
CPU time 1.44 seconds
Started Jun 02 01:44:01 PM PDT 24
Finished Jun 02 01:44:02 PM PDT 24
Peak memory 197036 kb
Host smart-645fe263-e418-46b8-b46b-e2a66395e3fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185825937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3185825937
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2094537261
Short name T588
Test name
Test status
Simulation time 32031337 ps
CPU time 1.37 seconds
Started Jun 02 01:43:59 PM PDT 24
Finished Jun 02 01:44:01 PM PDT 24
Peak memory 196288 kb
Host smart-3951735d-dea7-4d23-968c-8f842f7bba03
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094537261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2094537261
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3109336564
Short name T455
Test name
Test status
Simulation time 670622654 ps
CPU time 3.26 seconds
Started Jun 02 01:44:00 PM PDT 24
Finished Jun 02 01:44:04 PM PDT 24
Peak memory 197212 kb
Host smart-3232e908-9947-457a-95c2-2bd3cc63a83d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109336564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3109336564
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.481721537
Short name T110
Test name
Test status
Simulation time 58286252 ps
CPU time 0.84 seconds
Started Jun 02 01:44:03 PM PDT 24
Finished Jun 02 01:44:04 PM PDT 24
Peak memory 196656 kb
Host smart-f266255a-ad2f-43cb-961d-563c7b3e27e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481721537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.481721537
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.887799851
Short name T688
Test name
Test status
Simulation time 25072204 ps
CPU time 0.73 seconds
Started Jun 02 01:44:01 PM PDT 24
Finished Jun 02 01:44:02 PM PDT 24
Peak memory 196180 kb
Host smart-b9083d63-2601-41aa-bfc7-1687801a54ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887799851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup
_pulldown.887799851
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2340405307
Short name T607
Test name
Test status
Simulation time 324724749 ps
CPU time 5.1 seconds
Started Jun 02 01:44:00 PM PDT 24
Finished Jun 02 01:44:06 PM PDT 24
Peak memory 197960 kb
Host smart-f28ef574-2ce9-4e69-bc43-9cea87fc89d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340405307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2340405307
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.916266270
Short name T488
Test name
Test status
Simulation time 160659076 ps
CPU time 1.37 seconds
Started Jun 02 01:44:01 PM PDT 24
Finished Jun 02 01:44:03 PM PDT 24
Peak memory 195704 kb
Host smart-95a49f33-19d1-47aa-a331-4d33fdff1a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916266270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.916266270
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2700433101
Short name T406
Test name
Test status
Simulation time 233520619 ps
CPU time 1.18 seconds
Started Jun 02 01:44:02 PM PDT 24
Finished Jun 02 01:44:03 PM PDT 24
Peak memory 196364 kb
Host smart-844540c8-2762-429d-b152-4bf70ae344e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700433101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2700433101
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2624079629
Short name T559
Test name
Test status
Simulation time 42211134592 ps
CPU time 143.93 seconds
Started Jun 02 01:43:59 PM PDT 24
Finished Jun 02 01:46:24 PM PDT 24
Peak memory 198116 kb
Host smart-30a7ff41-8ea7-4577-bb16-3415ffce6720
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624079629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2624079629
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.888932746
Short name T629
Test name
Test status
Simulation time 47637652 ps
CPU time 0.59 seconds
Started Jun 02 01:42:32 PM PDT 24
Finished Jun 02 01:42:33 PM PDT 24
Peak memory 194556 kb
Host smart-e88c9eed-96e9-4a3a-92f6-28147dbd25ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888932746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.888932746
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1242130620
Short name T660
Test name
Test status
Simulation time 23777196 ps
CPU time 0.76 seconds
Started Jun 02 01:42:26 PM PDT 24
Finished Jun 02 01:42:28 PM PDT 24
Peak memory 195344 kb
Host smart-9d1cf99a-7018-42e3-98ba-9afcfa47f345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242130620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1242130620
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3700866196
Short name T307
Test name
Test status
Simulation time 789857186 ps
CPU time 26.93 seconds
Started Jun 02 01:42:28 PM PDT 24
Finished Jun 02 01:42:56 PM PDT 24
Peak memory 197936 kb
Host smart-2cbbea17-49b6-4660-9c29-85fd6abbd05a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700866196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3700866196
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3986500813
Short name T215
Test name
Test status
Simulation time 52969703 ps
CPU time 0.91 seconds
Started Jun 02 01:42:29 PM PDT 24
Finished Jun 02 01:42:31 PM PDT 24
Peak memory 196416 kb
Host smart-f54c1beb-70bf-43eb-bd30-74db68d1c1da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986500813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3986500813
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1076884084
Short name T674
Test name
Test status
Simulation time 61008927 ps
CPU time 1.05 seconds
Started Jun 02 01:42:27 PM PDT 24
Finished Jun 02 01:42:29 PM PDT 24
Peak memory 195792 kb
Host smart-3d174df7-54ec-481b-8f43-ab4e82f82a1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076884084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1076884084
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3818652399
Short name T329
Test name
Test status
Simulation time 289250545 ps
CPU time 2.95 seconds
Started Jun 02 01:42:29 PM PDT 24
Finished Jun 02 01:42:33 PM PDT 24
Peak memory 198008 kb
Host smart-9d192325-6d77-4da6-8ba0-c8bd82e9be67
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818652399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3818652399
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3340631888
Short name T360
Test name
Test status
Simulation time 265470329 ps
CPU time 2.93 seconds
Started Jun 02 01:42:27 PM PDT 24
Finished Jun 02 01:42:31 PM PDT 24
Peak memory 196944 kb
Host smart-bb2e9a29-d468-4ac8-9f6b-c4f5beaa078e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340631888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3340631888
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.4266427114
Short name T548
Test name
Test status
Simulation time 72082202 ps
CPU time 0.69 seconds
Started Jun 02 01:42:28 PM PDT 24
Finished Jun 02 01:42:29 PM PDT 24
Peak memory 195036 kb
Host smart-27242353-e783-4b0e-a0a9-7baac476c942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266427114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.4266427114
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1615669702
Short name T509
Test name
Test status
Simulation time 50684388 ps
CPU time 0.63 seconds
Started Jun 02 01:42:28 PM PDT 24
Finished Jun 02 01:42:29 PM PDT 24
Peak memory 195032 kb
Host smart-7018782a-cd17-451b-bbfc-86c19680d69d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615669702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1615669702
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2785008564
Short name T706
Test name
Test status
Simulation time 204103784 ps
CPU time 2.77 seconds
Started Jun 02 01:42:28 PM PDT 24
Finished Jun 02 01:42:32 PM PDT 24
Peak memory 197956 kb
Host smart-bf5a21bf-ab1f-4f31-9076-61743ea55a16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785008564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2785008564
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3724360242
Short name T34
Test name
Test status
Simulation time 86257041 ps
CPU time 0.97 seconds
Started Jun 02 01:42:30 PM PDT 24
Finished Jun 02 01:42:31 PM PDT 24
Peak memory 214960 kb
Host smart-c3455462-f48f-4239-8d72-2029d938885d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724360242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3724360242
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1060108922
Short name T495
Test name
Test status
Simulation time 30905535 ps
CPU time 0.95 seconds
Started Jun 02 01:42:29 PM PDT 24
Finished Jun 02 01:42:30 PM PDT 24
Peak memory 196720 kb
Host smart-8f5ae58a-c6b9-4bcd-ae22-2b1b041da3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060108922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1060108922
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2807633460
Short name T554
Test name
Test status
Simulation time 43726069 ps
CPU time 1.17 seconds
Started Jun 02 01:42:32 PM PDT 24
Finished Jun 02 01:42:34 PM PDT 24
Peak memory 195756 kb
Host smart-7587e9db-023f-44d5-9a6e-fdabfb92e0c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807633460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2807633460
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2560836599
Short name T23
Test name
Test status
Simulation time 5672806512 ps
CPU time 146.87 seconds
Started Jun 02 01:42:28 PM PDT 24
Finished Jun 02 01:44:55 PM PDT 24
Peak memory 198100 kb
Host smart-151fba2d-c459-4ddb-aef9-6d245a004356
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560836599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2560836599
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2923114990
Short name T337
Test name
Test status
Simulation time 31036232 ps
CPU time 0.58 seconds
Started Jun 02 01:43:59 PM PDT 24
Finished Jun 02 01:44:00 PM PDT 24
Peak memory 194780 kb
Host smart-ece03816-0fee-4fdb-872c-6cbf6f2b7a12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923114990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2923114990
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1358213935
Short name T538
Test name
Test status
Simulation time 145738520 ps
CPU time 0.8 seconds
Started Jun 02 01:44:03 PM PDT 24
Finished Jun 02 01:44:04 PM PDT 24
Peak memory 195488 kb
Host smart-fd52659f-a3c2-4f1c-98a2-bc5e3b0ecc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358213935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1358213935
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.291891144
Short name T604
Test name
Test status
Simulation time 132928609 ps
CPU time 5.42 seconds
Started Jun 02 01:43:59 PM PDT 24
Finished Jun 02 01:44:04 PM PDT 24
Peak memory 195868 kb
Host smart-8c654276-b8c2-4a18-9662-12a90952b8ae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291891144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.291891144
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2039267177
Short name T702
Test name
Test status
Simulation time 196926029 ps
CPU time 0.82 seconds
Started Jun 02 01:44:01 PM PDT 24
Finished Jun 02 01:44:02 PM PDT 24
Peak memory 195288 kb
Host smart-c83761fb-99cb-4606-b73c-f114a462f74b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039267177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2039267177
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.4218587795
Short name T680
Test name
Test status
Simulation time 237283663 ps
CPU time 0.85 seconds
Started Jun 02 01:43:58 PM PDT 24
Finished Jun 02 01:44:00 PM PDT 24
Peak memory 196276 kb
Host smart-1e684ef4-2ef0-4aad-8918-89111db0e1e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218587795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.4218587795
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1720614091
Short name T353
Test name
Test status
Simulation time 86913613 ps
CPU time 3.39 seconds
Started Jun 02 01:44:04 PM PDT 24
Finished Jun 02 01:44:07 PM PDT 24
Peak memory 198092 kb
Host smart-787051d8-25b7-4d40-9670-81a16bee06ab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720614091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1720614091
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2224535478
Short name T280
Test name
Test status
Simulation time 56983006 ps
CPU time 1.29 seconds
Started Jun 02 01:44:02 PM PDT 24
Finished Jun 02 01:44:04 PM PDT 24
Peak memory 196568 kb
Host smart-00d0b0c3-b45a-40a4-86f0-d3f07e01012c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224535478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2224535478
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.722347593
Short name T251
Test name
Test status
Simulation time 51128729 ps
CPU time 1.15 seconds
Started Jun 02 01:44:02 PM PDT 24
Finished Jun 02 01:44:04 PM PDT 24
Peak memory 195956 kb
Host smart-0e6110a0-ac04-43c0-8e05-7e10d04de51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722347593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.722347593
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3045292530
Short name T487
Test name
Test status
Simulation time 339552703 ps
CPU time 1.18 seconds
Started Jun 02 01:44:01 PM PDT 24
Finished Jun 02 01:44:03 PM PDT 24
Peak memory 196424 kb
Host smart-88ecf228-5c75-4545-a6ba-9873632c883f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045292530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3045292530
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2991175535
Short name T443
Test name
Test status
Simulation time 566130660 ps
CPU time 4.65 seconds
Started Jun 02 01:43:58 PM PDT 24
Finished Jun 02 01:44:03 PM PDT 24
Peak memory 197972 kb
Host smart-e6c59287-4844-4c80-8653-482ed939bbc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991175535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2991175535
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.213589387
Short name T606
Test name
Test status
Simulation time 70230718 ps
CPU time 1.38 seconds
Started Jun 02 01:44:01 PM PDT 24
Finished Jun 02 01:44:03 PM PDT 24
Peak memory 198000 kb
Host smart-ccb2ad28-00e5-4593-a80d-7a9749a9f3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213589387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.213589387
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1123786036
Short name T500
Test name
Test status
Simulation time 164586513 ps
CPU time 1.2 seconds
Started Jun 02 01:44:00 PM PDT 24
Finished Jun 02 01:44:02 PM PDT 24
Peak memory 195868 kb
Host smart-9bca261e-5657-4093-9007-83ff166292f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123786036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1123786036
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.290227920
Short name T327
Test name
Test status
Simulation time 71558964596 ps
CPU time 204.28 seconds
Started Jun 02 01:44:00 PM PDT 24
Finished Jun 02 01:47:24 PM PDT 24
Peak memory 198156 kb
Host smart-55f6e3b3-54da-4e01-bc1d-e46a39d8ad7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290227920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.290227920
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1507494671
Short name T575
Test name
Test status
Simulation time 82084106498 ps
CPU time 1755.32 seconds
Started Jun 02 01:44:00 PM PDT 24
Finished Jun 02 02:13:16 PM PDT 24
Peak memory 198180 kb
Host smart-7b2b082d-8400-4618-ab45-9b164139cdef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1507494671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1507494671
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1507579674
Short name T431
Test name
Test status
Simulation time 12483935 ps
CPU time 0.56 seconds
Started Jun 02 01:44:06 PM PDT 24
Finished Jun 02 01:44:07 PM PDT 24
Peak memory 194584 kb
Host smart-c31b01d5-6ea6-43dc-8c38-2ae7c8fedbd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507579674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1507579674
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3324219098
Short name T289
Test name
Test status
Simulation time 75256034 ps
CPU time 0.65 seconds
Started Jun 02 01:44:07 PM PDT 24
Finished Jun 02 01:44:08 PM PDT 24
Peak memory 194372 kb
Host smart-b015c3e6-4ad2-4d24-bd3f-6478f6fac869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324219098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3324219098
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2426616860
Short name T467
Test name
Test status
Simulation time 496980474 ps
CPU time 6.31 seconds
Started Jun 02 01:44:05 PM PDT 24
Finished Jun 02 01:44:12 PM PDT 24
Peak memory 196832 kb
Host smart-441a9785-f584-4661-a929-7398c8657a6b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426616860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2426616860
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2502806361
Short name T478
Test name
Test status
Simulation time 49767992 ps
CPU time 0.7 seconds
Started Jun 02 01:44:06 PM PDT 24
Finished Jun 02 01:44:07 PM PDT 24
Peak memory 194552 kb
Host smart-a37532a0-19b0-49f2-8753-422f11fa8510
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502806361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2502806361
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3887272068
Short name T603
Test name
Test status
Simulation time 84598561 ps
CPU time 0.82 seconds
Started Jun 02 01:44:09 PM PDT 24
Finished Jun 02 01:44:10 PM PDT 24
Peak memory 196180 kb
Host smart-49ba718e-4f38-457f-9390-85577ea37b6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887272068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3887272068
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.922828954
Short name T399
Test name
Test status
Simulation time 170842802 ps
CPU time 1.39 seconds
Started Jun 02 01:44:07 PM PDT 24
Finished Jun 02 01:44:08 PM PDT 24
Peak memory 196584 kb
Host smart-d8bc90df-f69a-422d-9187-cabf1b23d248
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922828954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.922828954
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2233437507
Short name T284
Test name
Test status
Simulation time 686769844 ps
CPU time 2.09 seconds
Started Jun 02 01:44:06 PM PDT 24
Finished Jun 02 01:44:08 PM PDT 24
Peak memory 198016 kb
Host smart-6928b506-31b3-4c45-87f0-cc683dce7486
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233437507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2233437507
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1323367784
Short name T255
Test name
Test status
Simulation time 158476671 ps
CPU time 0.87 seconds
Started Jun 02 01:44:07 PM PDT 24
Finished Jun 02 01:44:08 PM PDT 24
Peak memory 196620 kb
Host smart-cc5e7209-bd08-41ee-b660-f4075aee0f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323367784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1323367784
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3413572798
Short name T477
Test name
Test status
Simulation time 30300158 ps
CPU time 0.82 seconds
Started Jun 02 01:44:06 PM PDT 24
Finished Jun 02 01:44:08 PM PDT 24
Peak memory 196204 kb
Host smart-27ad5171-a47f-45ce-9305-75e5227e5633
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413572798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3413572798
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1085109736
Short name T16
Test name
Test status
Simulation time 326767664 ps
CPU time 5.3 seconds
Started Jun 02 01:44:06 PM PDT 24
Finished Jun 02 01:44:12 PM PDT 24
Peak memory 198124 kb
Host smart-1a16524a-a697-4284-9fa6-f0668390dfcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085109736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1085109736
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2200339487
Short name T456
Test name
Test status
Simulation time 26542185 ps
CPU time 0.84 seconds
Started Jun 02 01:44:00 PM PDT 24
Finished Jun 02 01:44:01 PM PDT 24
Peak memory 195472 kb
Host smart-78d4e444-607a-4298-8af7-69a98ca13cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200339487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2200339487
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2125651322
Short name T301
Test name
Test status
Simulation time 335162699 ps
CPU time 1.41 seconds
Started Jun 02 01:44:01 PM PDT 24
Finished Jun 02 01:44:02 PM PDT 24
Peak memory 197376 kb
Host smart-29b649f6-57c8-496d-8b00-a3eae4c3450a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125651322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2125651322
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2423895113
Short name T154
Test name
Test status
Simulation time 21553001645 ps
CPU time 144.08 seconds
Started Jun 02 01:44:06 PM PDT 24
Finished Jun 02 01:46:31 PM PDT 24
Peak memory 198084 kb
Host smart-3d5871ab-687c-437a-81d4-13b0a02d111e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423895113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2423895113
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.4164384823
Short name T246
Test name
Test status
Simulation time 12601388 ps
CPU time 0.58 seconds
Started Jun 02 01:44:10 PM PDT 24
Finished Jun 02 01:44:11 PM PDT 24
Peak memory 194008 kb
Host smart-983dd5c2-bfdf-4875-a2a0-ffaa1c44bb2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164384823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.4164384823
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3169085514
Short name T245
Test name
Test status
Simulation time 30701353 ps
CPU time 0.81 seconds
Started Jun 02 01:44:06 PM PDT 24
Finished Jun 02 01:44:08 PM PDT 24
Peak memory 196104 kb
Host smart-7a385799-d6e9-4928-a6ff-2e17cd816295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169085514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3169085514
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.771293036
Short name T626
Test name
Test status
Simulation time 827044836 ps
CPU time 28.46 seconds
Started Jun 02 01:44:10 PM PDT 24
Finished Jun 02 01:44:39 PM PDT 24
Peak memory 196944 kb
Host smart-f3ea2958-7456-44f1-bf57-709af91cc588
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771293036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stres
s.771293036
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1996635304
Short name T459
Test name
Test status
Simulation time 78835272 ps
CPU time 0.92 seconds
Started Jun 02 01:44:12 PM PDT 24
Finished Jun 02 01:44:13 PM PDT 24
Peak memory 196092 kb
Host smart-ed8faf25-c1ef-408f-ace3-2c916eeaaee3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996635304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1996635304
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3804862250
Short name T382
Test name
Test status
Simulation time 290627407 ps
CPU time 1.04 seconds
Started Jun 02 01:44:05 PM PDT 24
Finished Jun 02 01:44:06 PM PDT 24
Peak memory 195788 kb
Host smart-630425b3-847d-493c-9e74-901323efb032
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804862250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3804862250
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1137620099
Short name T357
Test name
Test status
Simulation time 344035476 ps
CPU time 3.4 seconds
Started Jun 02 01:44:14 PM PDT 24
Finished Jun 02 01:44:18 PM PDT 24
Peak memory 196316 kb
Host smart-e7012f92-292e-4385-9df4-1108e24dd7f5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137620099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1137620099
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3020459627
Short name T17
Test name
Test status
Simulation time 42719048 ps
CPU time 1.45 seconds
Started Jun 02 01:44:09 PM PDT 24
Finished Jun 02 01:44:10 PM PDT 24
Peak memory 196244 kb
Host smart-b3ba563a-aeee-437c-b3fa-0899bd4b7b9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020459627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3020459627
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1639366058
Short name T590
Test name
Test status
Simulation time 68108263 ps
CPU time 0.68 seconds
Started Jun 02 01:44:07 PM PDT 24
Finished Jun 02 01:44:08 PM PDT 24
Peak memory 194280 kb
Host smart-213ce75f-8168-4e2b-b206-22a3726daafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639366058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1639366058
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2096680319
Short name T708
Test name
Test status
Simulation time 228131232 ps
CPU time 1.17 seconds
Started Jun 02 01:44:06 PM PDT 24
Finished Jun 02 01:44:08 PM PDT 24
Peak memory 195992 kb
Host smart-da30ed37-177b-4109-b1c5-5485ca3739af
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096680319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2096680319
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1415458437
Short name T412
Test name
Test status
Simulation time 229762335 ps
CPU time 3.27 seconds
Started Jun 02 01:44:13 PM PDT 24
Finished Jun 02 01:44:16 PM PDT 24
Peak memory 197940 kb
Host smart-305af5be-9b05-41b3-86e8-b7d8eeb59494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415458437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1415458437
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2224815862
Short name T68
Test name
Test status
Simulation time 191616688 ps
CPU time 1.33 seconds
Started Jun 02 01:44:06 PM PDT 24
Finished Jun 02 01:44:08 PM PDT 24
Peak memory 195572 kb
Host smart-aee86118-0422-42eb-8bea-c399528aa9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224815862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2224815862
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2369698299
Short name T413
Test name
Test status
Simulation time 52666072 ps
CPU time 1.19 seconds
Started Jun 02 01:44:06 PM PDT 24
Finished Jun 02 01:44:08 PM PDT 24
Peak memory 195568 kb
Host smart-1206f260-4e98-4180-a0d2-e46562b13771
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369698299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2369698299
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3479744006
Short name T707
Test name
Test status
Simulation time 11744992610 ps
CPU time 44.8 seconds
Started Jun 02 01:44:11 PM PDT 24
Finished Jun 02 01:44:57 PM PDT 24
Peak memory 198152 kb
Host smart-edd06393-e257-4178-8853-9e066a037084
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479744006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3479744006
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.1886595388
Short name T29
Test name
Test status
Simulation time 31533164926 ps
CPU time 965.76 seconds
Started Jun 02 01:44:14 PM PDT 24
Finished Jun 02 02:00:20 PM PDT 24
Peak memory 198240 kb
Host smart-38d64755-9905-4a0d-b9f4-1a4c853afe70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1886595388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.1886595388
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1313980290
Short name T460
Test name
Test status
Simulation time 61274948 ps
CPU time 0.59 seconds
Started Jun 02 01:44:19 PM PDT 24
Finished Jun 02 01:44:20 PM PDT 24
Peak memory 194724 kb
Host smart-04624604-bdc6-4edf-bdbc-eca36b33b284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313980290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1313980290
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1483659965
Short name T227
Test name
Test status
Simulation time 63762967 ps
CPU time 0.71 seconds
Started Jun 02 01:44:14 PM PDT 24
Finished Jun 02 01:44:15 PM PDT 24
Peak memory 195512 kb
Host smart-0895b168-1cfd-4f68-9fd8-9ab88d3d18d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483659965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1483659965
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.523407550
Short name T26
Test name
Test status
Simulation time 226023179 ps
CPU time 3.62 seconds
Started Jun 02 01:44:11 PM PDT 24
Finished Jun 02 01:44:15 PM PDT 24
Peak memory 195836 kb
Host smart-d1b0c9d9-6c42-432f-a66f-57c30a501389
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523407550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stres
s.523407550
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2548606457
Short name T516
Test name
Test status
Simulation time 53796555 ps
CPU time 0.62 seconds
Started Jun 02 01:44:11 PM PDT 24
Finished Jun 02 01:44:12 PM PDT 24
Peak memory 194464 kb
Host smart-87133823-d0d7-4e4f-9b44-a29cab6cd27d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548606457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2548606457
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.21415916
Short name T504
Test name
Test status
Simulation time 60625943 ps
CPU time 1.04 seconds
Started Jun 02 01:44:13 PM PDT 24
Finished Jun 02 01:44:14 PM PDT 24
Peak memory 196000 kb
Host smart-8e96547c-c41c-4563-a69c-b7c026862365
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21415916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.21415916
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2580274972
Short name T676
Test name
Test status
Simulation time 41974759 ps
CPU time 1.69 seconds
Started Jun 02 01:44:14 PM PDT 24
Finished Jun 02 01:44:16 PM PDT 24
Peak memory 198096 kb
Host smart-f7b69960-2e9f-4f9f-808d-c13095bf317e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580274972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2580274972
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.208852282
Short name T657
Test name
Test status
Simulation time 211763138 ps
CPU time 1.85 seconds
Started Jun 02 01:44:14 PM PDT 24
Finished Jun 02 01:44:16 PM PDT 24
Peak memory 196180 kb
Host smart-fa9c4708-6651-47c3-86b9-575de3d605ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208852282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
208852282
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.4110464417
Short name T113
Test name
Test status
Simulation time 61117961 ps
CPU time 1.33 seconds
Started Jun 02 01:44:12 PM PDT 24
Finished Jun 02 01:44:13 PM PDT 24
Peak memory 196980 kb
Host smart-821a1918-a7ae-4163-8c84-ef94c36da7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110464417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.4110464417
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2408631278
Short name T526
Test name
Test status
Simulation time 81535878 ps
CPU time 0.97 seconds
Started Jun 02 01:44:12 PM PDT 24
Finished Jun 02 01:44:13 PM PDT 24
Peak memory 195800 kb
Host smart-0929d851-828a-464e-97ba-4e20b2144da1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408631278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2408631278
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1807956736
Short name T169
Test name
Test status
Simulation time 619618827 ps
CPU time 4.78 seconds
Started Jun 02 01:44:12 PM PDT 24
Finished Jun 02 01:44:17 PM PDT 24
Peak memory 197824 kb
Host smart-2e4f662a-6fe3-44eb-8a3a-4d5972116b50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807956736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1807956736
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2000477824
Short name T140
Test name
Test status
Simulation time 34079949 ps
CPU time 0.89 seconds
Started Jun 02 01:44:10 PM PDT 24
Finished Jun 02 01:44:11 PM PDT 24
Peak memory 196076 kb
Host smart-79eab44c-5910-4c31-956f-38292feb9c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000477824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2000477824
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.780138341
Short name T395
Test name
Test status
Simulation time 30731924 ps
CPU time 0.91 seconds
Started Jun 02 01:44:13 PM PDT 24
Finished Jun 02 01:44:14 PM PDT 24
Peak memory 195940 kb
Host smart-03f81691-09ff-41e6-a63c-f0252a6d2de5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780138341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.780138341
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2477587678
Short name T367
Test name
Test status
Simulation time 35427451857 ps
CPU time 152.4 seconds
Started Jun 02 01:44:21 PM PDT 24
Finished Jun 02 01:46:53 PM PDT 24
Peak memory 198192 kb
Host smart-54b73d82-80a7-4c8c-b62c-a07c77fddd08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477587678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2477587678
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1528846355
Short name T37
Test name
Test status
Simulation time 61785048 ps
CPU time 0.58 seconds
Started Jun 02 01:44:19 PM PDT 24
Finished Jun 02 01:44:20 PM PDT 24
Peak memory 193912 kb
Host smart-156ad3b4-9b55-4cb3-b8a9-984729fd557e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528846355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1528846355
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1888927365
Short name T304
Test name
Test status
Simulation time 26098172 ps
CPU time 0.69 seconds
Started Jun 02 01:44:21 PM PDT 24
Finished Jun 02 01:44:22 PM PDT 24
Peak memory 194080 kb
Host smart-32615c41-f213-42a2-9e3a-f6940bea977e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888927365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1888927365
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2783107349
Short name T640
Test name
Test status
Simulation time 1248753236 ps
CPU time 23.9 seconds
Started Jun 02 01:44:18 PM PDT 24
Finished Jun 02 01:44:43 PM PDT 24
Peak memory 197124 kb
Host smart-d8ea5d1e-72ab-4cd3-9cd8-6bd86012c59f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783107349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2783107349
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2562586325
Short name T20
Test name
Test status
Simulation time 307956970 ps
CPU time 0.97 seconds
Started Jun 02 01:44:21 PM PDT 24
Finished Jun 02 01:44:23 PM PDT 24
Peak memory 197256 kb
Host smart-57464157-5fd1-4453-9e66-15f5e3b48b50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562586325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2562586325
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.4010851612
Short name T556
Test name
Test status
Simulation time 45004392 ps
CPU time 1.15 seconds
Started Jun 02 01:44:21 PM PDT 24
Finished Jun 02 01:44:23 PM PDT 24
Peak memory 195932 kb
Host smart-71732e6f-af6b-4795-9eb6-8d8fb78339a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010851612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.4010851612
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.494874923
Short name T593
Test name
Test status
Simulation time 182508333 ps
CPU time 3.98 seconds
Started Jun 02 01:44:21 PM PDT 24
Finished Jun 02 01:44:26 PM PDT 24
Peak memory 198000 kb
Host smart-4340b492-8d89-4979-9f57-6730f758ac09
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494874923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.494874923
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.709389846
Short name T457
Test name
Test status
Simulation time 54035643 ps
CPU time 1.37 seconds
Started Jun 02 01:44:18 PM PDT 24
Finished Jun 02 01:44:19 PM PDT 24
Peak memory 195876 kb
Host smart-e9d0750d-48b5-42c6-a25f-ff113bfbed63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709389846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
709389846
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.345248999
Short name T369
Test name
Test status
Simulation time 15439059 ps
CPU time 0.69 seconds
Started Jun 02 01:44:19 PM PDT 24
Finished Jun 02 01:44:20 PM PDT 24
Peak memory 194332 kb
Host smart-734f64fc-5da9-4694-8527-c78809abce67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345248999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.345248999
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1430585153
Short name T129
Test name
Test status
Simulation time 90639787 ps
CPU time 1.13 seconds
Started Jun 02 01:44:21 PM PDT 24
Finished Jun 02 01:44:23 PM PDT 24
Peak memory 195796 kb
Host smart-cb490f77-0778-4325-a115-40344edbed3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430585153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1430585153
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.722578260
Short name T662
Test name
Test status
Simulation time 786496281 ps
CPU time 3.56 seconds
Started Jun 02 01:44:18 PM PDT 24
Finished Jun 02 01:44:22 PM PDT 24
Peak memory 197960 kb
Host smart-86f5359c-482b-4e0b-bc7d-c576171ae58a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722578260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.722578260
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2905452404
Short name T637
Test name
Test status
Simulation time 91108118 ps
CPU time 1.34 seconds
Started Jun 02 01:44:20 PM PDT 24
Finished Jun 02 01:44:22 PM PDT 24
Peak memory 196816 kb
Host smart-96c0425e-ce04-4536-9dd6-e6b2cb5c014b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905452404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2905452404
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.506797306
Short name T302
Test name
Test status
Simulation time 60818991 ps
CPU time 1.22 seconds
Started Jun 02 01:44:22 PM PDT 24
Finished Jun 02 01:44:24 PM PDT 24
Peak memory 196476 kb
Host smart-e24c8bc0-2726-401d-83f5-9b0a94f876df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506797306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.506797306
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1635441127
Short name T5
Test name
Test status
Simulation time 52024551472 ps
CPU time 138.12 seconds
Started Jun 02 01:44:17 PM PDT 24
Finished Jun 02 01:46:35 PM PDT 24
Peak memory 198340 kb
Host smart-513c3e38-8396-42f6-a678-e5fdaeffbac3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635441127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1635441127
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.4052420960
Short name T582
Test name
Test status
Simulation time 82537462894 ps
CPU time 1933.63 seconds
Started Jun 02 01:44:21 PM PDT 24
Finished Jun 02 02:16:35 PM PDT 24
Peak memory 198192 kb
Host smart-e0e4562e-9a24-4ec9-bdd8-47d985c87903
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4052420960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.4052420960
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3788710821
Short name T507
Test name
Test status
Simulation time 65792813 ps
CPU time 0.57 seconds
Started Jun 02 01:44:21 PM PDT 24
Finished Jun 02 01:44:21 PM PDT 24
Peak memory 194540 kb
Host smart-c6787042-74af-4a3f-ba97-889b044eed37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788710821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3788710821
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1221420404
Short name T474
Test name
Test status
Simulation time 117620581 ps
CPU time 0.75 seconds
Started Jun 02 01:44:21 PM PDT 24
Finished Jun 02 01:44:23 PM PDT 24
Peak memory 195360 kb
Host smart-7eb3ee3b-80cf-4648-8984-6c82be7cedc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221420404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1221420404
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.4176496655
Short name T529
Test name
Test status
Simulation time 1568788995 ps
CPU time 22.29 seconds
Started Jun 02 01:44:21 PM PDT 24
Finished Jun 02 01:44:43 PM PDT 24
Peak memory 197136 kb
Host smart-f0e89a4e-fdbf-456b-bed7-5ecd644555d2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176496655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.4176496655
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1282338982
Short name T46
Test name
Test status
Simulation time 226718146 ps
CPU time 0.97 seconds
Started Jun 02 01:44:22 PM PDT 24
Finished Jun 02 01:44:24 PM PDT 24
Peak memory 196968 kb
Host smart-1c911e88-f334-43af-87f1-f1906ca1ad7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282338982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1282338982
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1999381125
Short name T407
Test name
Test status
Simulation time 53965561 ps
CPU time 0.93 seconds
Started Jun 02 01:44:19 PM PDT 24
Finished Jun 02 01:44:20 PM PDT 24
Peak memory 196804 kb
Host smart-d1b1b940-70ec-4a04-bae8-f739280dcb7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999381125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1999381125
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1229317744
Short name T387
Test name
Test status
Simulation time 225013751 ps
CPU time 2.4 seconds
Started Jun 02 01:44:19 PM PDT 24
Finished Jun 02 01:44:22 PM PDT 24
Peak memory 198084 kb
Host smart-26668930-2ee4-407c-bb63-5297959e2dc0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229317744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1229317744
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1899837967
Short name T501
Test name
Test status
Simulation time 48947184 ps
CPU time 1.11 seconds
Started Jun 02 01:44:20 PM PDT 24
Finished Jun 02 01:44:22 PM PDT 24
Peak memory 195624 kb
Host smart-d5cef356-91f7-43d4-ac07-fd5356cdfb2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899837967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1899837967
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2973053749
Short name T692
Test name
Test status
Simulation time 102841638 ps
CPU time 0.61 seconds
Started Jun 02 01:44:19 PM PDT 24
Finished Jun 02 01:44:20 PM PDT 24
Peak memory 194168 kb
Host smart-1d812a56-0c55-4b7f-be66-e15c9b05a3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973053749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2973053749
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.967503690
Short name T222
Test name
Test status
Simulation time 20604273 ps
CPU time 0.77 seconds
Started Jun 02 01:44:17 PM PDT 24
Finished Jun 02 01:44:18 PM PDT 24
Peak memory 195584 kb
Host smart-886db45b-39f2-434f-94c2-183958bbfc64
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967503690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.967503690
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1163675420
Short name T480
Test name
Test status
Simulation time 3395372371 ps
CPU time 4.08 seconds
Started Jun 02 01:44:21 PM PDT 24
Finished Jun 02 01:44:25 PM PDT 24
Peak memory 198084 kb
Host smart-23466dff-ebd5-42be-b83c-30702a98c569
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163675420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1163675420
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.4150685496
Short name T261
Test name
Test status
Simulation time 53958647 ps
CPU time 1.1 seconds
Started Jun 02 01:44:18 PM PDT 24
Finished Jun 02 01:44:20 PM PDT 24
Peak memory 195708 kb
Host smart-f4bc123a-736e-4344-81ad-1ac2e072ed07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150685496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.4150685496
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3032019100
Short name T189
Test name
Test status
Simulation time 24767005 ps
CPU time 0.83 seconds
Started Jun 02 01:44:21 PM PDT 24
Finished Jun 02 01:44:22 PM PDT 24
Peak memory 196120 kb
Host smart-189e0b32-53a4-4e27-aca7-ce21549c6832
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032019100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3032019100
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3238804747
Short name T331
Test name
Test status
Simulation time 15363011583 ps
CPU time 163.85 seconds
Started Jun 02 01:44:19 PM PDT 24
Finished Jun 02 01:47:03 PM PDT 24
Peak memory 198112 kb
Host smart-29bd33ef-fe73-44dd-91ca-69abb8ffcd9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238804747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3238804747
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.2206258089
Short name T57
Test name
Test status
Simulation time 61603814902 ps
CPU time 1884.69 seconds
Started Jun 02 01:44:21 PM PDT 24
Finished Jun 02 02:15:46 PM PDT 24
Peak memory 198196 kb
Host smart-1929128d-ff33-4357-bf03-ebb171722f2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2206258089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.2206258089
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.94219833
Short name T247
Test name
Test status
Simulation time 13557000 ps
CPU time 0.59 seconds
Started Jun 02 01:44:24 PM PDT 24
Finished Jun 02 01:44:25 PM PDT 24
Peak memory 194084 kb
Host smart-87ec56d7-141e-4e7b-a5b3-a10facd0fd17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94219833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.94219833
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1359029476
Short name T119
Test name
Test status
Simulation time 50669740 ps
CPU time 0.65 seconds
Started Jun 02 01:44:20 PM PDT 24
Finished Jun 02 01:44:21 PM PDT 24
Peak memory 194024 kb
Host smart-92590754-a6a5-4570-9db0-af5b3af97b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359029476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1359029476
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1618948720
Short name T308
Test name
Test status
Simulation time 456748062 ps
CPU time 4 seconds
Started Jun 02 01:44:24 PM PDT 24
Finished Jun 02 01:44:28 PM PDT 24
Peak memory 196648 kb
Host smart-f1bd3148-8abe-4e14-9ba1-65efa980677d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618948720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1618948720
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2790745034
Short name T345
Test name
Test status
Simulation time 241902567 ps
CPU time 0.73 seconds
Started Jun 02 01:44:22 PM PDT 24
Finished Jun 02 01:44:23 PM PDT 24
Peak memory 195840 kb
Host smart-2df6ad4d-ce2e-4b8d-82fc-3d45c104325d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790745034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2790745034
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.41454649
Short name T316
Test name
Test status
Simulation time 113150372 ps
CPU time 0.89 seconds
Started Jun 02 01:44:21 PM PDT 24
Finished Jun 02 01:44:23 PM PDT 24
Peak memory 195444 kb
Host smart-2e1fe2e0-a91e-4082-8fb9-53824c5c8929
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41454649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.41454649
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.190057550
Short name T205
Test name
Test status
Simulation time 77360352 ps
CPU time 3.21 seconds
Started Jun 02 01:44:25 PM PDT 24
Finished Jun 02 01:44:29 PM PDT 24
Peak memory 198348 kb
Host smart-36f3963e-011d-4acd-a185-3934e45eccab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190057550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.190057550
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3599983647
Short name T346
Test name
Test status
Simulation time 157221864 ps
CPU time 3.4 seconds
Started Jun 02 01:44:21 PM PDT 24
Finished Jun 02 01:44:25 PM PDT 24
Peak memory 198036 kb
Host smart-7988f7ae-6cb4-464e-affd-6393bd46f3c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599983647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3599983647
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1161110988
Short name T631
Test name
Test status
Simulation time 54271350 ps
CPU time 1.06 seconds
Started Jun 02 01:44:20 PM PDT 24
Finished Jun 02 01:44:22 PM PDT 24
Peak memory 195892 kb
Host smart-296abfa7-c2de-438f-b6dc-29cbdbe14448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161110988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1161110988
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3414935824
Short name T673
Test name
Test status
Simulation time 134921102 ps
CPU time 1.33 seconds
Started Jun 02 01:44:22 PM PDT 24
Finished Jun 02 01:44:23 PM PDT 24
Peak memory 196964 kb
Host smart-e0a77e9b-90ad-40a9-b876-9aaa3e9e6193
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414935824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3414935824
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3804907948
Short name T555
Test name
Test status
Simulation time 194788521 ps
CPU time 4.85 seconds
Started Jun 02 01:44:24 PM PDT 24
Finished Jun 02 01:44:30 PM PDT 24
Peak memory 197884 kb
Host smart-228e410e-198e-4138-9cb1-e183af230764
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804907948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3804907948
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2156908791
Short name T427
Test name
Test status
Simulation time 112175811 ps
CPU time 0.98 seconds
Started Jun 02 01:44:17 PM PDT 24
Finished Jun 02 01:44:19 PM PDT 24
Peak memory 197112 kb
Host smart-41af8556-a8c8-45fe-85c8-07ca88d15b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156908791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2156908791
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1896945272
Short name T45
Test name
Test status
Simulation time 30011771 ps
CPU time 0.9 seconds
Started Jun 02 01:44:15 PM PDT 24
Finished Jun 02 01:44:17 PM PDT 24
Peak memory 195684 kb
Host smart-db346cc6-66a6-436b-bafa-a5f4255c7f5e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896945272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1896945272
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1496995363
Short name T533
Test name
Test status
Simulation time 13685961171 ps
CPU time 195.58 seconds
Started Jun 02 01:44:26 PM PDT 24
Finished Jun 02 01:47:42 PM PDT 24
Peak memory 198180 kb
Host smart-0a1b1e14-79e8-4e69-b033-ac1b7a0ca59a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496995363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1496995363
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3743016269
Short name T278
Test name
Test status
Simulation time 33912134 ps
CPU time 0.55 seconds
Started Jun 02 01:44:25 PM PDT 24
Finished Jun 02 01:44:26 PM PDT 24
Peak memory 194532 kb
Host smart-c3367996-349e-4367-868f-4a94ca234b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743016269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3743016269
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1999792581
Short name T144
Test name
Test status
Simulation time 68890479 ps
CPU time 0.93 seconds
Started Jun 02 01:44:23 PM PDT 24
Finished Jun 02 01:44:25 PM PDT 24
Peak memory 196588 kb
Host smart-01ac691c-36ed-433c-8585-447dd5c76f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999792581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1999792581
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2349162596
Short name T656
Test name
Test status
Simulation time 677840295 ps
CPU time 3.69 seconds
Started Jun 02 01:44:23 PM PDT 24
Finished Jun 02 01:44:27 PM PDT 24
Peak memory 196676 kb
Host smart-861fdb25-0ae4-4e57-a04e-88d2eef8dec6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349162596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2349162596
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1551805263
Short name T414
Test name
Test status
Simulation time 50852137 ps
CPU time 0.82 seconds
Started Jun 02 01:44:25 PM PDT 24
Finished Jun 02 01:44:26 PM PDT 24
Peak memory 196604 kb
Host smart-7bfc5ead-e108-4797-8378-1f99d7c7c383
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551805263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1551805263
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2562852402
Short name T523
Test name
Test status
Simulation time 41272621 ps
CPU time 0.91 seconds
Started Jun 02 01:44:25 PM PDT 24
Finished Jun 02 01:44:27 PM PDT 24
Peak memory 197540 kb
Host smart-ba83bb8d-3f15-4730-a494-b18caab45ed2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562852402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2562852402
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1497504902
Short name T545
Test name
Test status
Simulation time 189360240 ps
CPU time 1.42 seconds
Started Jun 02 01:44:23 PM PDT 24
Finished Jun 02 01:44:25 PM PDT 24
Peak memory 196336 kb
Host smart-f957df2d-be00-47a1-adff-59c3615b3ac4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497504902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1497504902
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3041139285
Short name T696
Test name
Test status
Simulation time 203037119 ps
CPU time 2.9 seconds
Started Jun 02 01:44:23 PM PDT 24
Finished Jun 02 01:44:27 PM PDT 24
Peak memory 196940 kb
Host smart-a30ec846-71e5-4b43-be08-ddc8d5ece757
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041139285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3041139285
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.4186049994
Short name T290
Test name
Test status
Simulation time 306803687 ps
CPU time 1.05 seconds
Started Jun 02 01:44:26 PM PDT 24
Finished Jun 02 01:44:27 PM PDT 24
Peak memory 196684 kb
Host smart-b78bff8b-f625-4e37-a8df-24f203b68bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186049994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.4186049994
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1001865779
Short name T208
Test name
Test status
Simulation time 20222225 ps
CPU time 0.68 seconds
Started Jun 02 01:44:24 PM PDT 24
Finished Jun 02 01:44:25 PM PDT 24
Peak memory 195432 kb
Host smart-894a2b73-cbbb-47ed-9b3d-87b4351f3781
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001865779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1001865779
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3144946648
Short name T514
Test name
Test status
Simulation time 319562160 ps
CPU time 2.85 seconds
Started Jun 02 01:44:25 PM PDT 24
Finished Jun 02 01:44:28 PM PDT 24
Peak memory 197972 kb
Host smart-4242fbd5-a94b-485f-acf8-fd491f5fafd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144946648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3144946648
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1043021113
Short name T281
Test name
Test status
Simulation time 29649317 ps
CPU time 0.91 seconds
Started Jun 02 01:44:24 PM PDT 24
Finished Jun 02 01:44:25 PM PDT 24
Peak memory 196136 kb
Host smart-1e8acf17-2596-422c-a228-5f79745f9017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043021113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1043021113
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.30332233
Short name T19
Test name
Test status
Simulation time 263680554 ps
CPU time 0.97 seconds
Started Jun 02 01:44:22 PM PDT 24
Finished Jun 02 01:44:23 PM PDT 24
Peak memory 196284 kb
Host smart-67d74899-b7a4-41d4-8677-95ae73d26547
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30332233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.30332233
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1462922353
Short name T571
Test name
Test status
Simulation time 7473517954 ps
CPU time 141.94 seconds
Started Jun 02 01:44:24 PM PDT 24
Finished Jun 02 01:46:46 PM PDT 24
Peak memory 198216 kb
Host smart-595c8318-2352-412c-af08-6b333e677559
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462922353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1462922353
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.2424089073
Short name T58
Test name
Test status
Simulation time 33190340266 ps
CPU time 533.25 seconds
Started Jun 02 01:44:23 PM PDT 24
Finished Jun 02 01:53:16 PM PDT 24
Peak memory 198168 kb
Host smart-aea5114d-7859-4490-b735-f63e45317889
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2424089073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.2424089073
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.4017568528
Short name T164
Test name
Test status
Simulation time 12681142 ps
CPU time 0.58 seconds
Started Jun 02 01:44:24 PM PDT 24
Finished Jun 02 01:44:25 PM PDT 24
Peak memory 194584 kb
Host smart-06b2a480-fa8f-4ef7-a9eb-c47803752b6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017568528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.4017568528
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3777852149
Short name T563
Test name
Test status
Simulation time 19889701 ps
CPU time 0.7 seconds
Started Jun 02 01:44:23 PM PDT 24
Finished Jun 02 01:44:24 PM PDT 24
Peak memory 195868 kb
Host smart-01c91aef-5abc-429c-8e10-a10b2faa728f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777852149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3777852149
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.59964521
Short name T168
Test name
Test status
Simulation time 204811746 ps
CPU time 9.21 seconds
Started Jun 02 01:44:22 PM PDT 24
Finished Jun 02 01:44:32 PM PDT 24
Peak memory 196900 kb
Host smart-523e058c-c76c-40fd-ac8d-8c6c6c506790
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59964521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stress
.59964521
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.4132923172
Short name T486
Test name
Test status
Simulation time 184218512 ps
CPU time 1.08 seconds
Started Jun 02 01:44:26 PM PDT 24
Finished Jun 02 01:44:27 PM PDT 24
Peak memory 196568 kb
Host smart-42168df4-0cd6-48ed-9654-901a7b023617
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132923172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.4132923172
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.308865699
Short name T547
Test name
Test status
Simulation time 98871039 ps
CPU time 1.31 seconds
Started Jun 02 01:44:29 PM PDT 24
Finished Jun 02 01:44:30 PM PDT 24
Peak memory 197184 kb
Host smart-8bb08634-5f04-41bb-991b-b9af2ee6a5e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308865699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.308865699
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2353081749
Short name T109
Test name
Test status
Simulation time 168377192 ps
CPU time 1.86 seconds
Started Jun 02 01:44:23 PM PDT 24
Finished Jun 02 01:44:25 PM PDT 24
Peak memory 198056 kb
Host smart-af828f19-7012-443b-ac7d-abf3213b4d8a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353081749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2353081749
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2573293051
Short name T234
Test name
Test status
Simulation time 364217051 ps
CPU time 2.81 seconds
Started Jun 02 01:44:24 PM PDT 24
Finished Jun 02 01:44:28 PM PDT 24
Peak memory 197076 kb
Host smart-c86812af-ff24-450b-83fb-d23bbe42a312
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573293051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2573293051
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1724073869
Short name T489
Test name
Test status
Simulation time 66954898 ps
CPU time 1.18 seconds
Started Jun 02 01:44:24 PM PDT 24
Finished Jun 02 01:44:26 PM PDT 24
Peak memory 197016 kb
Host smart-7aa1b99b-d2c6-4eac-a95a-8a9cb6513229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724073869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1724073869
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.944288806
Short name T372
Test name
Test status
Simulation time 96043793 ps
CPU time 1.02 seconds
Started Jun 02 01:44:26 PM PDT 24
Finished Jun 02 01:44:27 PM PDT 24
Peak memory 196044 kb
Host smart-afd8eead-7ef1-4c11-9018-47bb664983fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944288806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.944288806
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2717562342
Short name T531
Test name
Test status
Simulation time 140898922 ps
CPU time 5.25 seconds
Started Jun 02 01:44:25 PM PDT 24
Finished Jun 02 01:44:31 PM PDT 24
Peak memory 197964 kb
Host smart-31d8cf74-2b45-48b0-8e73-db61a714f0ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717562342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2717562342
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1583038225
Short name T300
Test name
Test status
Simulation time 461469756 ps
CPU time 1.03 seconds
Started Jun 02 01:44:23 PM PDT 24
Finished Jun 02 01:44:25 PM PDT 24
Peak memory 196380 kb
Host smart-51de7f48-f250-4eaa-aac8-5931710e79bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583038225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1583038225
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1784787779
Short name T196
Test name
Test status
Simulation time 103445266 ps
CPU time 1.51 seconds
Started Jun 02 01:44:24 PM PDT 24
Finished Jun 02 01:44:26 PM PDT 24
Peak memory 198264 kb
Host smart-c9d5d7f5-1253-4cac-893f-f6ccfd57ac7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784787779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1784787779
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1490323352
Short name T594
Test name
Test status
Simulation time 56845682997 ps
CPU time 164.37 seconds
Started Jun 02 01:44:24 PM PDT 24
Finished Jun 02 01:47:09 PM PDT 24
Peak memory 198124 kb
Host smart-c57de9c5-f646-4e80-ae16-057ecd7c1e25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490323352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1490323352
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1413401035
Short name T147
Test name
Test status
Simulation time 45254660 ps
CPU time 0.58 seconds
Started Jun 02 01:44:29 PM PDT 24
Finished Jun 02 01:44:30 PM PDT 24
Peak memory 193892 kb
Host smart-1ef306cf-1acd-45fa-89d0-0f991905b763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413401035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1413401035
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1049923386
Short name T589
Test name
Test status
Simulation time 100615213 ps
CPU time 0.75 seconds
Started Jun 02 01:44:32 PM PDT 24
Finished Jun 02 01:44:34 PM PDT 24
Peak memory 194232 kb
Host smart-396e6716-e7da-4092-b669-ae1d3d83cf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049923386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1049923386
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3378764762
Short name T285
Test name
Test status
Simulation time 576417459 ps
CPU time 5.02 seconds
Started Jun 02 01:44:30 PM PDT 24
Finished Jun 02 01:44:36 PM PDT 24
Peak memory 197056 kb
Host smart-b5910b0f-e601-4ae4-a7be-b9123d22d65b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378764762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3378764762
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3034164312
Short name T4
Test name
Test status
Simulation time 293514618 ps
CPU time 1 seconds
Started Jun 02 01:44:32 PM PDT 24
Finished Jun 02 01:44:34 PM PDT 24
Peak memory 196640 kb
Host smart-75601838-1490-487b-a877-7ded158cd96a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034164312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3034164312
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.52017488
Short name T184
Test name
Test status
Simulation time 287857078 ps
CPU time 1.28 seconds
Started Jun 02 01:44:32 PM PDT 24
Finished Jun 02 01:44:34 PM PDT 24
Peak memory 196648 kb
Host smart-acda7109-d8e9-446f-8065-ddd8cbf7fe33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52017488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.52017488
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2831283562
Short name T343
Test name
Test status
Simulation time 45929900 ps
CPU time 1.75 seconds
Started Jun 02 01:44:32 PM PDT 24
Finished Jun 02 01:44:35 PM PDT 24
Peak memory 198088 kb
Host smart-73d5c89e-82be-4e26-a727-1e7e90cf070e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831283562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2831283562
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3780941940
Short name T577
Test name
Test status
Simulation time 245281151 ps
CPU time 2.31 seconds
Started Jun 02 01:44:31 PM PDT 24
Finished Jun 02 01:44:33 PM PDT 24
Peak memory 198056 kb
Host smart-fb134b14-e3ab-4c47-bf30-3e104f8716e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780941940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3780941940
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.558730198
Short name T388
Test name
Test status
Simulation time 26983868 ps
CPU time 0.97 seconds
Started Jun 02 01:44:27 PM PDT 24
Finished Jun 02 01:44:29 PM PDT 24
Peak memory 196044 kb
Host smart-2be81d59-993a-45d7-8154-96a8da69ffbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558730198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.558730198
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1332935969
Short name T204
Test name
Test status
Simulation time 35190422 ps
CPU time 1.28 seconds
Started Jun 02 01:44:23 PM PDT 24
Finished Jun 02 01:44:25 PM PDT 24
Peak memory 196988 kb
Host smart-44180f21-5535-46cf-a609-f819cab6e720
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332935969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1332935969
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.4278634915
Short name T715
Test name
Test status
Simulation time 56955241 ps
CPU time 1.14 seconds
Started Jun 02 01:44:30 PM PDT 24
Finished Jun 02 01:44:31 PM PDT 24
Peak memory 197824 kb
Host smart-37a2cba5-9972-4006-b09c-f71fdf96195e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278634915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.4278634915
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1875011985
Short name T118
Test name
Test status
Simulation time 110075318 ps
CPU time 0.91 seconds
Started Jun 02 01:44:24 PM PDT 24
Finished Jun 02 01:44:26 PM PDT 24
Peak memory 195596 kb
Host smart-bacf85d7-6ef9-4a14-a029-7fd2a369374c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875011985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1875011985
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2365601363
Short name T686
Test name
Test status
Simulation time 62680694 ps
CPU time 1.1 seconds
Started Jun 02 01:44:24 PM PDT 24
Finished Jun 02 01:44:26 PM PDT 24
Peak memory 195528 kb
Host smart-c5e213d8-1704-49c6-8e7f-2771ad9042cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365601363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2365601363
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1698647465
Short name T356
Test name
Test status
Simulation time 6660242127 ps
CPU time 86.53 seconds
Started Jun 02 01:44:32 PM PDT 24
Finished Jun 02 01:46:00 PM PDT 24
Peak memory 198156 kb
Host smart-77bfce13-40c0-4575-8729-fb0d8ec819d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698647465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1698647465
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.3391129690
Short name T691
Test name
Test status
Simulation time 68948705546 ps
CPU time 1604.17 seconds
Started Jun 02 01:44:32 PM PDT 24
Finished Jun 02 02:11:17 PM PDT 24
Peak memory 198224 kb
Host smart-f872198d-2e3d-4571-a560-ec09d9bb49c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3391129690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.3391129690
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1543108236
Short name T458
Test name
Test status
Simulation time 23946133 ps
CPU time 0.55 seconds
Started Jun 02 01:42:35 PM PDT 24
Finished Jun 02 01:42:36 PM PDT 24
Peak memory 193900 kb
Host smart-998b4474-60c9-4f22-89ff-08bb18f0ee49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543108236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1543108236
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3488823176
Short name T596
Test name
Test status
Simulation time 30506570 ps
CPU time 0.7 seconds
Started Jun 02 01:42:27 PM PDT 24
Finished Jun 02 01:42:29 PM PDT 24
Peak memory 194672 kb
Host smart-67a39586-3668-4018-b5ab-e8a05ff65914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488823176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3488823176
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1004796894
Short name T447
Test name
Test status
Simulation time 474389201 ps
CPU time 7.75 seconds
Started Jun 02 01:42:30 PM PDT 24
Finished Jun 02 01:42:38 PM PDT 24
Peak memory 197968 kb
Host smart-4587b3e4-6c55-433c-b342-6c3ca7209b05
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004796894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1004796894
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1403105076
Short name T64
Test name
Test status
Simulation time 131819700 ps
CPU time 1 seconds
Started Jun 02 01:42:35 PM PDT 24
Finished Jun 02 01:42:37 PM PDT 24
Peak memory 196548 kb
Host smart-798862b8-6f6a-4aa9-b378-22c25b28c710
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403105076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1403105076
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.433345792
Short name T512
Test name
Test status
Simulation time 489186599 ps
CPU time 1.5 seconds
Started Jun 02 01:42:27 PM PDT 24
Finished Jun 02 01:42:29 PM PDT 24
Peak memory 195808 kb
Host smart-b0d8882e-7687-4003-a065-5134867b0e83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433345792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.433345792
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2779579124
Short name T260
Test name
Test status
Simulation time 382305114 ps
CPU time 3.29 seconds
Started Jun 02 01:42:29 PM PDT 24
Finished Jun 02 01:42:33 PM PDT 24
Peak memory 197836 kb
Host smart-0344acf1-f900-46b2-9598-11c767665dd0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779579124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2779579124
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1530023471
Short name T569
Test name
Test status
Simulation time 107703467 ps
CPU time 2.28 seconds
Started Jun 02 01:42:27 PM PDT 24
Finished Jun 02 01:42:30 PM PDT 24
Peak memory 195940 kb
Host smart-fe1dd069-f843-4093-aef5-83772ed74d58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530023471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1530023471
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1326254898
Short name T334
Test name
Test status
Simulation time 92249475 ps
CPU time 1.1 seconds
Started Jun 02 01:42:28 PM PDT 24
Finished Jun 02 01:42:29 PM PDT 24
Peak memory 196052 kb
Host smart-92a19d95-e3f0-4c3c-97b7-4205f2272b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326254898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1326254898
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3263639962
Short name T543
Test name
Test status
Simulation time 201634584 ps
CPU time 1.08 seconds
Started Jun 02 01:42:28 PM PDT 24
Finished Jun 02 01:42:30 PM PDT 24
Peak memory 195852 kb
Host smart-7c616680-6073-48cd-9a54-56436dbfee42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263639962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3263639962
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2986267007
Short name T679
Test name
Test status
Simulation time 622926218 ps
CPU time 3.06 seconds
Started Jun 02 01:42:31 PM PDT 24
Finished Jun 02 01:42:34 PM PDT 24
Peak memory 197948 kb
Host smart-45cdd5e9-e1ad-4b5d-8aae-249bb805dbe7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986267007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2986267007
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.163501440
Short name T292
Test name
Test status
Simulation time 246171344 ps
CPU time 1.13 seconds
Started Jun 02 01:42:26 PM PDT 24
Finished Jun 02 01:42:28 PM PDT 24
Peak memory 196460 kb
Host smart-1864e52c-471f-46b0-9388-3103162354a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163501440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.163501440
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2718562142
Short name T306
Test name
Test status
Simulation time 164190211 ps
CPU time 0.91 seconds
Started Jun 02 01:42:28 PM PDT 24
Finished Jun 02 01:42:30 PM PDT 24
Peak memory 196388 kb
Host smart-ef979cfa-925f-44c4-83fb-d2010ce1e2a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718562142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2718562142
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1986396548
Short name T401
Test name
Test status
Simulation time 33869566142 ps
CPU time 184.77 seconds
Started Jun 02 01:42:33 PM PDT 24
Finished Jun 02 01:45:38 PM PDT 24
Peak memory 198192 kb
Host smart-d3ede219-987b-42cd-92c9-b8b991eecee4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986396548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1986396548
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1463435600
Short name T60
Test name
Test status
Simulation time 14468698167 ps
CPU time 243.05 seconds
Started Jun 02 01:42:33 PM PDT 24
Finished Jun 02 01:46:36 PM PDT 24
Peak memory 198200 kb
Host smart-089f439b-b903-413d-8ca6-39de65fa2049
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1463435600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1463435600
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2471214711
Short name T471
Test name
Test status
Simulation time 28620854 ps
CPU time 0.61 seconds
Started Jun 02 01:42:33 PM PDT 24
Finished Jun 02 01:42:34 PM PDT 24
Peak memory 193888 kb
Host smart-ce6780cb-f1fb-4e8a-b368-518c099f5572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471214711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2471214711
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2087843801
Short name T120
Test name
Test status
Simulation time 17326079 ps
CPU time 0.63 seconds
Started Jun 02 01:42:37 PM PDT 24
Finished Jun 02 01:42:38 PM PDT 24
Peak memory 194728 kb
Host smart-6553e311-28bf-425c-ba1a-8de4a931127d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087843801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2087843801
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1681477726
Short name T323
Test name
Test status
Simulation time 2691508675 ps
CPU time 24.12 seconds
Started Jun 02 01:42:35 PM PDT 24
Finished Jun 02 01:43:00 PM PDT 24
Peak memory 196600 kb
Host smart-bc4b4618-4825-47d2-b4e9-2abd4fd9d731
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681477726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1681477726
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2522872205
Short name T314
Test name
Test status
Simulation time 336414171 ps
CPU time 1.09 seconds
Started Jun 02 01:42:36 PM PDT 24
Finished Jun 02 01:42:38 PM PDT 24
Peak memory 197860 kb
Host smart-3568001e-202f-4a83-97a0-3aecaad3573a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522872205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2522872205
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.4248064809
Short name T580
Test name
Test status
Simulation time 111601947 ps
CPU time 1.15 seconds
Started Jun 02 01:42:36 PM PDT 24
Finished Jun 02 01:42:38 PM PDT 24
Peak memory 195912 kb
Host smart-16006606-518d-4d7c-9dea-43f2ffcb801d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248064809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.4248064809
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.893062583
Short name T328
Test name
Test status
Simulation time 308717106 ps
CPU time 2.48 seconds
Started Jun 02 01:42:34 PM PDT 24
Finished Jun 02 01:42:37 PM PDT 24
Peak memory 198016 kb
Host smart-e5e2ceb8-2a0d-40ad-98cf-f32526864441
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893062583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.893062583
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1129493857
Short name T521
Test name
Test status
Simulation time 1041542441 ps
CPU time 2.7 seconds
Started Jun 02 01:42:35 PM PDT 24
Finished Jun 02 01:42:39 PM PDT 24
Peak memory 197208 kb
Host smart-944223e6-7f6d-4d1a-ad7b-e3e8c5185abc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129493857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1129493857
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2966304064
Short name T442
Test name
Test status
Simulation time 284956513 ps
CPU time 1.3 seconds
Started Jun 02 01:42:36 PM PDT 24
Finished Jun 02 01:42:38 PM PDT 24
Peak memory 198016 kb
Host smart-9f0e307b-bf99-4389-a46f-4f966e021c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966304064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2966304064
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.575604031
Short name T622
Test name
Test status
Simulation time 270610289 ps
CPU time 0.98 seconds
Started Jun 02 01:42:35 PM PDT 24
Finished Jun 02 01:42:36 PM PDT 24
Peak memory 196052 kb
Host smart-e912f9f5-57c3-4e4c-8618-b3143164e86b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575604031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.575604031
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2817887807
Short name T573
Test name
Test status
Simulation time 1385823127 ps
CPU time 4.02 seconds
Started Jun 02 01:42:34 PM PDT 24
Finished Jun 02 01:42:38 PM PDT 24
Peak memory 197964 kb
Host smart-df456ddd-d5bc-45db-ae12-ec97ee76369c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817887807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2817887807
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3050658381
Short name T309
Test name
Test status
Simulation time 112893105 ps
CPU time 1.07 seconds
Started Jun 02 01:42:36 PM PDT 24
Finished Jun 02 01:42:37 PM PDT 24
Peak memory 195524 kb
Host smart-22d9fed5-e13c-4c74-97f3-0042e5d71693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050658381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3050658381
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3453147668
Short name T685
Test name
Test status
Simulation time 310809784 ps
CPU time 1.32 seconds
Started Jun 02 01:42:33 PM PDT 24
Finished Jun 02 01:42:35 PM PDT 24
Peak memory 195500 kb
Host smart-71455e29-42c4-4b09-bc01-227929b904ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453147668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3453147668
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3019251651
Short name T358
Test name
Test status
Simulation time 24190242100 ps
CPU time 150.41 seconds
Started Jun 02 01:42:35 PM PDT 24
Finished Jun 02 01:45:06 PM PDT 24
Peak memory 198144 kb
Host smart-7a982b2c-6e83-4c85-8dee-093b5098d065
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019251651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3019251651
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.850055613
Short name T185
Test name
Test status
Simulation time 10538547 ps
CPU time 0.55 seconds
Started Jun 02 01:42:33 PM PDT 24
Finished Jun 02 01:42:34 PM PDT 24
Peak memory 192736 kb
Host smart-e309d2ba-86e5-4a69-b809-5a101c43dfaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850055613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.850055613
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1847779750
Short name T364
Test name
Test status
Simulation time 676806258 ps
CPU time 0.89 seconds
Started Jun 02 01:42:34 PM PDT 24
Finished Jun 02 01:42:36 PM PDT 24
Peak memory 195696 kb
Host smart-298bd695-128e-4842-893f-9534d8ac1086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847779750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1847779750
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1048409942
Short name T383
Test name
Test status
Simulation time 158939101 ps
CPU time 4.81 seconds
Started Jun 02 01:42:38 PM PDT 24
Finished Jun 02 01:42:43 PM PDT 24
Peak memory 195548 kb
Host smart-13547071-7759-40ec-93c0-880e880687f1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048409942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1048409942
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1161513639
Short name T377
Test name
Test status
Simulation time 991122816 ps
CPU time 1.07 seconds
Started Jun 02 01:42:36 PM PDT 24
Finished Jun 02 01:42:37 PM PDT 24
Peak memory 196280 kb
Host smart-62c512db-d98e-4957-8550-86b4deccbaea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161513639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1161513639
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.4052230031
Short name T13
Test name
Test status
Simulation time 295461971 ps
CPU time 1.21 seconds
Started Jun 02 01:42:36 PM PDT 24
Finished Jun 02 01:42:38 PM PDT 24
Peak memory 196572 kb
Host smart-ef6e0bd5-09c0-42d0-944e-28d1ea96f4f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052230031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.4052230031
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.4089833732
Short name T163
Test name
Test status
Simulation time 346110903 ps
CPU time 3.47 seconds
Started Jun 02 01:42:36 PM PDT 24
Finished Jun 02 01:42:40 PM PDT 24
Peak memory 198024 kb
Host smart-26b61d93-f35f-49fd-b6ee-2dc5d12cf766
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089833732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.4089833732
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1475154690
Short name T664
Test name
Test status
Simulation time 37309775 ps
CPU time 0.98 seconds
Started Jun 02 01:42:36 PM PDT 24
Finished Jun 02 01:42:38 PM PDT 24
Peak memory 196296 kb
Host smart-bc140128-fc8f-4da2-89c9-e6ab9ea0109b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475154690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1475154690
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3986217996
Short name T534
Test name
Test status
Simulation time 79058868 ps
CPU time 1.33 seconds
Started Jun 02 01:42:34 PM PDT 24
Finished Jun 02 01:42:35 PM PDT 24
Peak memory 195776 kb
Host smart-725c6d2b-77d0-4a7c-8e3a-fa271be95a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986217996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3986217996
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2853123516
Short name T318
Test name
Test status
Simulation time 51557664 ps
CPU time 1.09 seconds
Started Jun 02 01:42:33 PM PDT 24
Finished Jun 02 01:42:35 PM PDT 24
Peak memory 195972 kb
Host smart-b3857af5-f917-431d-88ff-ec7c59a7a670
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853123516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2853123516
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2505824719
Short name T259
Test name
Test status
Simulation time 491981247 ps
CPU time 4.69 seconds
Started Jun 02 01:42:33 PM PDT 24
Finished Jun 02 01:42:38 PM PDT 24
Peak memory 197908 kb
Host smart-8e0ed4c1-6d39-4c27-93c2-c93083abd69e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505824719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2505824719
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3347755693
Short name T693
Test name
Test status
Simulation time 322467121 ps
CPU time 1.14 seconds
Started Jun 02 01:42:35 PM PDT 24
Finished Jun 02 01:42:37 PM PDT 24
Peak memory 195440 kb
Host smart-821d3e25-b10c-4bc8-b92c-f7695181d477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347755693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3347755693
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3944837632
Short name T340
Test name
Test status
Simulation time 148526283 ps
CPU time 0.94 seconds
Started Jun 02 01:42:36 PM PDT 24
Finished Jun 02 01:42:37 PM PDT 24
Peak memory 195604 kb
Host smart-c4bfd3d9-daf9-428e-8cf6-8490f28dfcad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944837632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3944837632
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.8461456
Short name T3
Test name
Test status
Simulation time 38139867973 ps
CPU time 102.62 seconds
Started Jun 02 01:42:34 PM PDT 24
Finished Jun 02 01:44:17 PM PDT 24
Peak memory 198168 kb
Host smart-eaa000b1-0a05-451e-8cf1-ced25775c731
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8461456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TES
T_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio
_stress_all.8461456
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.277652831
Short name T210
Test name
Test status
Simulation time 14274359 ps
CPU time 0.58 seconds
Started Jun 02 01:42:39 PM PDT 24
Finished Jun 02 01:42:40 PM PDT 24
Peak memory 194044 kb
Host smart-9f812448-7d30-40cc-ad75-e9490f84f220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277652831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.277652831
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.977367701
Short name T661
Test name
Test status
Simulation time 95271192 ps
CPU time 0.85 seconds
Started Jun 02 01:42:38 PM PDT 24
Finished Jun 02 01:42:39 PM PDT 24
Peak memory 196360 kb
Host smart-b53a6fb6-4510-40aa-a81c-05dd7e4c3130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977367701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.977367701
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2762172971
Short name T530
Test name
Test status
Simulation time 313580985 ps
CPU time 11.57 seconds
Started Jun 02 01:42:41 PM PDT 24
Finished Jun 02 01:42:53 PM PDT 24
Peak memory 197992 kb
Host smart-460b23e8-02f5-4e01-af3c-c8263c948713
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762172971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2762172971
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1416708813
Short name T659
Test name
Test status
Simulation time 182670822 ps
CPU time 0.79 seconds
Started Jun 02 01:42:39 PM PDT 24
Finished Jun 02 01:42:40 PM PDT 24
Peak memory 195772 kb
Host smart-6d73c51c-85fe-4cd2-a339-9b70dc6191c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416708813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1416708813
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2563363852
Short name T149
Test name
Test status
Simulation time 153605737 ps
CPU time 1.24 seconds
Started Jun 02 01:42:41 PM PDT 24
Finished Jun 02 01:42:42 PM PDT 24
Peak memory 196108 kb
Host smart-7764122f-dcaa-4fed-9f99-49e679529458
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563363852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2563363852
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1406772352
Short name T237
Test name
Test status
Simulation time 109681543 ps
CPU time 2.3 seconds
Started Jun 02 01:42:38 PM PDT 24
Finished Jun 02 01:42:41 PM PDT 24
Peak memory 198012 kb
Host smart-cffba33a-3436-42b9-a01e-503322e32145
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406772352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1406772352
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.164235592
Short name T562
Test name
Test status
Simulation time 564536048 ps
CPU time 2.77 seconds
Started Jun 02 01:42:38 PM PDT 24
Finished Jun 02 01:42:41 PM PDT 24
Peak memory 197140 kb
Host smart-2daef379-7239-4ffb-a3dc-1aeadc85f0b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164235592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.164235592
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3271497650
Short name T22
Test name
Test status
Simulation time 98759598 ps
CPU time 1.15 seconds
Started Jun 02 01:42:37 PM PDT 24
Finished Jun 02 01:42:39 PM PDT 24
Peak memory 196576 kb
Host smart-836b95cc-1efa-42ba-8727-49c022ec85f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271497650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3271497650
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.4276527416
Short name T633
Test name
Test status
Simulation time 116035735 ps
CPU time 0.8 seconds
Started Jun 02 01:42:41 PM PDT 24
Finished Jun 02 01:42:43 PM PDT 24
Peak memory 196340 kb
Host smart-ce9a7aa1-227e-46f6-a87f-4ea435513685
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276527416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.4276527416
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2659585021
Short name T233
Test name
Test status
Simulation time 117731039 ps
CPU time 5.37 seconds
Started Jun 02 01:42:40 PM PDT 24
Finished Jun 02 01:42:46 PM PDT 24
Peak memory 197928 kb
Host smart-6c41c742-9cea-4048-87be-84d7b29fcd4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659585021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2659585021
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1250267016
Short name T472
Test name
Test status
Simulation time 139830444 ps
CPU time 0.78 seconds
Started Jun 02 01:42:37 PM PDT 24
Finished Jun 02 01:42:38 PM PDT 24
Peak memory 195284 kb
Host smart-96c81394-78ca-45ec-8207-a4b3609caebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250267016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1250267016
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2458968637
Short name T711
Test name
Test status
Simulation time 44935833 ps
CPU time 0.95 seconds
Started Jun 02 01:42:43 PM PDT 24
Finished Jun 02 01:42:44 PM PDT 24
Peak memory 195468 kb
Host smart-808e1638-60a5-40e2-b29e-69b942f8a1df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458968637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2458968637
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.905076073
Short name T221
Test name
Test status
Simulation time 6765000035 ps
CPU time 91.48 seconds
Started Jun 02 01:42:40 PM PDT 24
Finished Jun 02 01:44:12 PM PDT 24
Peak memory 198112 kb
Host smart-78217b97-b1f5-42d2-b34b-d056ba638713
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905076073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.905076073
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.1228463499
Short name T56
Test name
Test status
Simulation time 293042857069 ps
CPU time 1719.33 seconds
Started Jun 02 01:42:39 PM PDT 24
Finished Jun 02 02:11:19 PM PDT 24
Peak memory 198188 kb
Host smart-64aecfb9-b29e-405a-a991-d4641a8080c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1228463499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.1228463499
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2472682141
Short name T584
Test name
Test status
Simulation time 102436499 ps
CPU time 0.55 seconds
Started Jun 02 01:42:40 PM PDT 24
Finished Jun 02 01:42:42 PM PDT 24
Peak memory 194012 kb
Host smart-7732db2d-1c6e-4879-aedb-92c53f842c9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472682141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2472682141
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1428474583
Short name T376
Test name
Test status
Simulation time 77525218 ps
CPU time 0.72 seconds
Started Jun 02 01:42:39 PM PDT 24
Finished Jun 02 01:42:40 PM PDT 24
Peak memory 194924 kb
Host smart-dca6817a-6acf-4774-be43-f7e35e8a85fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428474583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1428474583
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3167753762
Short name T130
Test name
Test status
Simulation time 1204016342 ps
CPU time 10.56 seconds
Started Jun 02 01:42:43 PM PDT 24
Finished Jun 02 01:42:54 PM PDT 24
Peak memory 195504 kb
Host smart-41f593d8-ac36-48e0-a182-5e35f54f878b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167753762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3167753762
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.4175842033
Short name T178
Test name
Test status
Simulation time 29749520 ps
CPU time 0.72 seconds
Started Jun 02 01:42:39 PM PDT 24
Finished Jun 02 01:42:41 PM PDT 24
Peak memory 194692 kb
Host smart-0dea95d0-4dce-45ec-98a7-57e948cdf272
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175842033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.4175842033
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1502795528
Short name T128
Test name
Test status
Simulation time 151342758 ps
CPU time 0.93 seconds
Started Jun 02 01:42:40 PM PDT 24
Finished Jun 02 01:42:42 PM PDT 24
Peak memory 195772 kb
Host smart-8bd100fd-3f7b-476c-98c3-75d9e94faad6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502795528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1502795528
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1832052166
Short name T183
Test name
Test status
Simulation time 1802709938 ps
CPU time 3.59 seconds
Started Jun 02 01:42:40 PM PDT 24
Finished Jun 02 01:42:44 PM PDT 24
Peak memory 198040 kb
Host smart-ebabb6cd-44f5-48a7-b862-325955bc1572
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832052166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1832052166
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.996469140
Short name T172
Test name
Test status
Simulation time 65388361 ps
CPU time 2.22 seconds
Started Jun 02 01:42:40 PM PDT 24
Finished Jun 02 01:42:43 PM PDT 24
Peak memory 197024 kb
Host smart-3e44a763-a14f-4477-9573-ef16f4c8271d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996469140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.996469140
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3792288209
Short name T167
Test name
Test status
Simulation time 100504378 ps
CPU time 0.8 seconds
Started Jun 02 01:42:39 PM PDT 24
Finished Jun 02 01:42:40 PM PDT 24
Peak memory 197336 kb
Host smart-de52e84d-52da-4cd4-b313-4a4a4933d3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792288209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3792288209
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2879352762
Short name T294
Test name
Test status
Simulation time 35571838 ps
CPU time 0.91 seconds
Started Jun 02 01:42:37 PM PDT 24
Finished Jun 02 01:42:39 PM PDT 24
Peak memory 196640 kb
Host smart-e0760349-bdf9-412f-afbe-6f4bb8727eda
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879352762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2879352762
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.4200323446
Short name T524
Test name
Test status
Simulation time 59941579 ps
CPU time 1.27 seconds
Started Jun 02 01:42:40 PM PDT 24
Finished Jun 02 01:42:42 PM PDT 24
Peak memory 197896 kb
Host smart-61804b66-5473-4d27-a8ce-101dd7599c35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200323446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.4200323446
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.720640323
Short name T123
Test name
Test status
Simulation time 121801509 ps
CPU time 1.11 seconds
Started Jun 02 01:42:41 PM PDT 24
Finished Jun 02 01:42:42 PM PDT 24
Peak memory 195736 kb
Host smart-2b3f1326-bb0b-4baf-9ae3-07fd9738a55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720640323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.720640323
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.389970421
Short name T397
Test name
Test status
Simulation time 576167691 ps
CPU time 1.25 seconds
Started Jun 02 01:42:42 PM PDT 24
Finished Jun 02 01:42:43 PM PDT 24
Peak memory 196636 kb
Host smart-18217f8c-d218-4539-ae1a-7f076a3c3f37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389970421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.389970421
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3713639106
Short name T493
Test name
Test status
Simulation time 20016412644 ps
CPU time 122.93 seconds
Started Jun 02 01:42:41 PM PDT 24
Finished Jun 02 01:44:45 PM PDT 24
Peak memory 198116 kb
Host smart-a5395f11-98ef-489f-b71a-b947994b19de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713639106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3713639106
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.3908330922
Short name T665
Test name
Test status
Simulation time 32539400788 ps
CPU time 201.84 seconds
Started Jun 02 01:42:38 PM PDT 24
Finished Jun 02 01:46:01 PM PDT 24
Peak memory 198144 kb
Host smart-1f4e5564-f6b1-49f2-896f-3be805249af3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3908330922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.3908330922
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2684384074
Short name T845
Test name
Test status
Simulation time 48548470 ps
CPU time 0.85 seconds
Started Jun 02 01:41:40 PM PDT 24
Finished Jun 02 01:41:42 PM PDT 24
Peak memory 195608 kb
Host smart-8bc49373-898d-4172-af0d-09ebb853598d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2684384074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2684384074
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.458761935
Short name T901
Test name
Test status
Simulation time 67316011 ps
CPU time 1.32 seconds
Started Jun 02 01:41:44 PM PDT 24
Finished Jun 02 01:41:46 PM PDT 24
Peak memory 197172 kb
Host smart-58c8786c-29c5-4930-a3bb-6fbeb7533be2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458761935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.458761935
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1460785157
Short name T862
Test name
Test status
Simulation time 169555975 ps
CPU time 1.18 seconds
Started Jun 02 01:41:46 PM PDT 24
Finished Jun 02 01:41:48 PM PDT 24
Peak memory 196944 kb
Host smart-ac8642dd-9c18-4ba5-9f1d-397ecda88c5e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1460785157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1460785157
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1407570483
Short name T895
Test name
Test status
Simulation time 97001119 ps
CPU time 1.44 seconds
Started Jun 02 01:41:48 PM PDT 24
Finished Jun 02 01:41:49 PM PDT 24
Peak memory 196956 kb
Host smart-7af15de2-f50b-4732-a337-7eec84562290
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407570483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1407570483
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2973359543
Short name T898
Test name
Test status
Simulation time 27279197 ps
CPU time 0.85 seconds
Started Jun 02 01:41:48 PM PDT 24
Finished Jun 02 01:41:49 PM PDT 24
Peak memory 195712 kb
Host smart-9be3b006-5f64-4314-900a-f5ce3755bb66
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2973359543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2973359543
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.778295992
Short name T849
Test name
Test status
Simulation time 208899562 ps
CPU time 1.13 seconds
Started Jun 02 01:41:47 PM PDT 24
Finished Jun 02 01:41:49 PM PDT 24
Peak memory 198432 kb
Host smart-993551a6-2419-414e-9740-a87fcc72de72
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778295992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.778295992
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.4081450321
Short name T938
Test name
Test status
Simulation time 45389209 ps
CPU time 1.25 seconds
Started Jun 02 01:41:51 PM PDT 24
Finished Jun 02 01:41:53 PM PDT 24
Peak memory 197012 kb
Host smart-044adc95-1841-4ad0-8cb8-4bbdfb238543
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4081450321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.4081450321
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2118784428
Short name T851
Test name
Test status
Simulation time 62651355 ps
CPU time 1.13 seconds
Started Jun 02 01:41:51 PM PDT 24
Finished Jun 02 01:41:53 PM PDT 24
Peak memory 196640 kb
Host smart-428caa3d-ff77-4c22-a840-1456a41d5d5d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118784428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2118784428
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.850269103
Short name T848
Test name
Test status
Simulation time 614062950 ps
CPU time 1.02 seconds
Started Jun 02 01:41:51 PM PDT 24
Finished Jun 02 01:41:53 PM PDT 24
Peak memory 198124 kb
Host smart-6c1c6613-5d9b-482f-9526-a14270958486
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=850269103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.850269103
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1294847647
Short name T878
Test name
Test status
Simulation time 104562161 ps
CPU time 1.39 seconds
Started Jun 02 01:41:51 PM PDT 24
Finished Jun 02 01:41:53 PM PDT 24
Peak memory 198212 kb
Host smart-01a5985d-00f3-476f-9fb2-693f59cbec54
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294847647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1294847647
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3440558515
Short name T850
Test name
Test status
Simulation time 231218335 ps
CPU time 1.21 seconds
Started Jun 02 01:41:53 PM PDT 24
Finished Jun 02 01:41:55 PM PDT 24
Peak memory 196736 kb
Host smart-ec953263-d101-47d4-b22a-f4d220c81ccf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3440558515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3440558515
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3071200357
Short name T896
Test name
Test status
Simulation time 77152713 ps
CPU time 1.18 seconds
Started Jun 02 01:41:50 PM PDT 24
Finished Jun 02 01:41:52 PM PDT 24
Peak memory 196112 kb
Host smart-70b40a60-d68b-4c34-8d52-237e74ce8f14
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071200357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3071200357
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3454608085
Short name T873
Test name
Test status
Simulation time 70128260 ps
CPU time 0.78 seconds
Started Jun 02 01:41:53 PM PDT 24
Finished Jun 02 01:41:54 PM PDT 24
Peak memory 195668 kb
Host smart-238bf20c-a0d6-4c96-a686-1c0b3178a216
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3454608085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3454608085
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1251257317
Short name T940
Test name
Test status
Simulation time 505831100 ps
CPU time 1.4 seconds
Started Jun 02 01:41:52 PM PDT 24
Finished Jun 02 01:41:53 PM PDT 24
Peak memory 198244 kb
Host smart-8fe0ea13-6fda-4430-bb4a-865abbe0760b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251257317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1251257317
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3099819191
Short name T900
Test name
Test status
Simulation time 141602603 ps
CPU time 1.36 seconds
Started Jun 02 01:41:51 PM PDT 24
Finished Jun 02 01:41:53 PM PDT 24
Peak memory 196976 kb
Host smart-08c13858-9145-42ff-a593-e0a184ff1ece
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3099819191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3099819191
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2561547897
Short name T871
Test name
Test status
Simulation time 152206232 ps
CPU time 0.88 seconds
Started Jun 02 01:41:51 PM PDT 24
Finished Jun 02 01:41:52 PM PDT 24
Peak memory 195824 kb
Host smart-47de00d6-7327-4a90-b187-25f585025c9b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561547897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2561547897
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.855842604
Short name T926
Test name
Test status
Simulation time 37495734 ps
CPU time 1.11 seconds
Started Jun 02 01:41:51 PM PDT 24
Finished Jun 02 01:41:53 PM PDT 24
Peak memory 196108 kb
Host smart-c31d374c-6b89-43fe-bee2-3ebad1a7d2d7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=855842604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.855842604
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2365741577
Short name T899
Test name
Test status
Simulation time 23057583 ps
CPU time 0.76 seconds
Started Jun 02 01:41:52 PM PDT 24
Finished Jun 02 01:41:53 PM PDT 24
Peak memory 196320 kb
Host smart-a06f28d9-809c-442b-8989-2981451476c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365741577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2365741577
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2498107705
Short name T929
Test name
Test status
Simulation time 38421487 ps
CPU time 1.1 seconds
Started Jun 02 01:41:51 PM PDT 24
Finished Jun 02 01:41:53 PM PDT 24
Peak memory 197804 kb
Host smart-28d1df3b-0dbf-48f3-bbde-80db35b7d22c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2498107705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2498107705
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3865398235
Short name T857
Test name
Test status
Simulation time 98355709 ps
CPU time 0.79 seconds
Started Jun 02 01:41:51 PM PDT 24
Finished Jun 02 01:41:53 PM PDT 24
Peak memory 196440 kb
Host smart-4c1206be-5653-4c60-8594-a1c1667f65f6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865398235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3865398235
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.612884198
Short name T869
Test name
Test status
Simulation time 37593496 ps
CPU time 1.22 seconds
Started Jun 02 01:41:51 PM PDT 24
Finished Jun 02 01:41:53 PM PDT 24
Peak memory 197148 kb
Host smart-53ae658b-20f9-46fb-8cbf-d47965352ce0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=612884198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.612884198
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3547968332
Short name T922
Test name
Test status
Simulation time 173978377 ps
CPU time 1.31 seconds
Started Jun 02 01:41:52 PM PDT 24
Finished Jun 02 01:41:54 PM PDT 24
Peak memory 198248 kb
Host smart-3b48ea11-9255-4302-8f9e-ed4323cc8d70
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547968332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3547968332
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2619581747
Short name T870
Test name
Test status
Simulation time 129354608 ps
CPU time 1.15 seconds
Started Jun 02 01:41:52 PM PDT 24
Finished Jun 02 01:41:53 PM PDT 24
Peak memory 195844 kb
Host smart-05bd77e1-c2af-4e9f-bfce-8b28f3f2b9d2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2619581747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2619581747
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2609272320
Short name T864
Test name
Test status
Simulation time 747478830 ps
CPU time 1.3 seconds
Started Jun 02 01:41:50 PM PDT 24
Finished Jun 02 01:41:52 PM PDT 24
Peak memory 197520 kb
Host smart-dc38ec7b-93c6-4b1e-9c15-89059650992f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609272320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2609272320
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.190953189
Short name T868
Test name
Test status
Simulation time 50457001 ps
CPU time 1.06 seconds
Started Jun 02 01:41:47 PM PDT 24
Finished Jun 02 01:41:49 PM PDT 24
Peak memory 196720 kb
Host smart-74d07e64-737d-40fd-a5c0-810b26a83103
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=190953189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.190953189
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1861314363
Short name T908
Test name
Test status
Simulation time 77830925 ps
CPU time 1.42 seconds
Started Jun 02 01:41:46 PM PDT 24
Finished Jun 02 01:41:48 PM PDT 24
Peak memory 198284 kb
Host smart-5b6c7ccf-82a8-4954-9dff-30bc8cffa68b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861314363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1861314363
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1202192634
Short name T906
Test name
Test status
Simulation time 174880781 ps
CPU time 1.33 seconds
Started Jun 02 01:41:50 PM PDT 24
Finished Jun 02 01:41:51 PM PDT 24
Peak memory 196816 kb
Host smart-41231451-1c8f-48ce-a93e-ab3ab49d275f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1202192634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1202192634
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.84487820
Short name T865
Test name
Test status
Simulation time 198143109 ps
CPU time 1.15 seconds
Started Jun 02 01:41:52 PM PDT 24
Finished Jun 02 01:41:54 PM PDT 24
Peak memory 196552 kb
Host smart-fb1d3bcc-0d60-47f7-9032-be670340f92e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84487820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.84487820
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1208835617
Short name T847
Test name
Test status
Simulation time 92505195 ps
CPU time 1.3 seconds
Started Jun 02 01:41:53 PM PDT 24
Finished Jun 02 01:41:55 PM PDT 24
Peak memory 196936 kb
Host smart-1eca52a2-d09b-4700-aa1c-d5ffdfeed852
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1208835617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1208835617
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.868679752
Short name T910
Test name
Test status
Simulation time 140713547 ps
CPU time 1.12 seconds
Started Jun 02 01:41:57 PM PDT 24
Finished Jun 02 01:41:59 PM PDT 24
Peak memory 196100 kb
Host smart-93be0984-9200-466c-bfa0-e1dc72d95bd0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868679752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.868679752
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.985616231
Short name T925
Test name
Test status
Simulation time 233696575 ps
CPU time 0.94 seconds
Started Jun 02 01:41:58 PM PDT 24
Finished Jun 02 01:41:59 PM PDT 24
Peak memory 196952 kb
Host smart-c3e8e168-6362-472b-b10c-a6bf06c40320
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=985616231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.985616231
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2254542393
Short name T854
Test name
Test status
Simulation time 126225660 ps
CPU time 1.02 seconds
Started Jun 02 01:41:57 PM PDT 24
Finished Jun 02 01:41:59 PM PDT 24
Peak memory 198224 kb
Host smart-50e3d102-d296-4b63-937c-27634c0de4e0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254542393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2254542393
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1165243338
Short name T860
Test name
Test status
Simulation time 116936344 ps
CPU time 1.23 seconds
Started Jun 02 01:41:57 PM PDT 24
Finished Jun 02 01:41:59 PM PDT 24
Peak memory 196612 kb
Host smart-05f154f9-c837-4531-b156-946f3c4b1ee1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1165243338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1165243338
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1276516478
Short name T890
Test name
Test status
Simulation time 108075050 ps
CPU time 1.03 seconds
Started Jun 02 01:41:57 PM PDT 24
Finished Jun 02 01:41:59 PM PDT 24
Peak memory 197584 kb
Host smart-d7667526-5026-46a5-92f3-d797e920a057
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276516478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1276516478
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.327111901
Short name T904
Test name
Test status
Simulation time 475927471 ps
CPU time 1.42 seconds
Started Jun 02 01:41:59 PM PDT 24
Finished Jun 02 01:42:01 PM PDT 24
Peak memory 196752 kb
Host smart-af052409-2cc9-4e08-a9aa-438704319d01
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=327111901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.327111901
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2169335390
Short name T939
Test name
Test status
Simulation time 81163462 ps
CPU time 1.34 seconds
Started Jun 02 01:41:58 PM PDT 24
Finished Jun 02 01:42:00 PM PDT 24
Peak memory 198196 kb
Host smart-65434461-e2a1-41e1-8f7d-c5cd60b444bb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169335390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2169335390
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3870679007
Short name T863
Test name
Test status
Simulation time 166493861 ps
CPU time 1.22 seconds
Started Jun 02 01:41:59 PM PDT 24
Finished Jun 02 01:42:01 PM PDT 24
Peak memory 197016 kb
Host smart-983db0b9-0c20-49b2-9bef-e5b3803bde1f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3870679007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3870679007
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2064332438
Short name T872
Test name
Test status
Simulation time 85123399 ps
CPU time 0.86 seconds
Started Jun 02 01:41:58 PM PDT 24
Finished Jun 02 01:41:59 PM PDT 24
Peak memory 196876 kb
Host smart-1b36435e-06f0-4b9f-99b9-61e3063abca3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064332438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2064332438
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.4186749898
Short name T928
Test name
Test status
Simulation time 135718224 ps
CPU time 0.84 seconds
Started Jun 02 01:41:59 PM PDT 24
Finished Jun 02 01:42:00 PM PDT 24
Peak memory 195488 kb
Host smart-158b584f-e190-4880-83db-f75ba7b6a728
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4186749898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.4186749898
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2984069510
Short name T843
Test name
Test status
Simulation time 187489933 ps
CPU time 1.18 seconds
Started Jun 02 01:41:56 PM PDT 24
Finished Jun 02 01:41:58 PM PDT 24
Peak memory 196724 kb
Host smart-5e35e3a5-8171-4f7f-9e8f-55feca35aad0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984069510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2984069510
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4024859948
Short name T846
Test name
Test status
Simulation time 29857572 ps
CPU time 0.81 seconds
Started Jun 02 01:41:58 PM PDT 24
Finished Jun 02 01:41:59 PM PDT 24
Peak memory 196284 kb
Host smart-d5938e4d-c518-495f-82b6-9909f0652570
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4024859948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.4024859948
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3471825996
Short name T887
Test name
Test status
Simulation time 186303944 ps
CPU time 0.92 seconds
Started Jun 02 01:41:57 PM PDT 24
Finished Jun 02 01:41:58 PM PDT 24
Peak memory 196980 kb
Host smart-ae47744a-d6d7-46b5-9b48-ac8bd1370202
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471825996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3471825996
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.699824140
Short name T856
Test name
Test status
Simulation time 55587547 ps
CPU time 1.21 seconds
Started Jun 02 01:41:58 PM PDT 24
Finished Jun 02 01:42:00 PM PDT 24
Peak memory 198208 kb
Host smart-4521b0d7-68ea-4799-a392-1ad808895fd5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=699824140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.699824140
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1010862264
Short name T881
Test name
Test status
Simulation time 80850475 ps
CPU time 1.31 seconds
Started Jun 02 01:41:58 PM PDT 24
Finished Jun 02 01:42:00 PM PDT 24
Peak memory 198236 kb
Host smart-d2866bbe-8683-485d-ad0e-9c3e14407f91
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010862264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1010862264
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.307407035
Short name T874
Test name
Test status
Simulation time 310116111 ps
CPU time 1.04 seconds
Started Jun 02 01:41:59 PM PDT 24
Finished Jun 02 01:42:00 PM PDT 24
Peak memory 196952 kb
Host smart-de5adbfe-836d-499f-bb9e-344c39806291
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=307407035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.307407035
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3581781113
Short name T916
Test name
Test status
Simulation time 171850671 ps
CPU time 1.25 seconds
Started Jun 02 01:41:59 PM PDT 24
Finished Jun 02 01:42:01 PM PDT 24
Peak memory 198232 kb
Host smart-c2f878ac-fe27-4463-89ae-fcbfc4f23c04
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581781113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3581781113
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.617367701
Short name T902
Test name
Test status
Simulation time 65627881 ps
CPU time 1.15 seconds
Started Jun 02 01:41:45 PM PDT 24
Finished Jun 02 01:41:47 PM PDT 24
Peak memory 196760 kb
Host smart-d3fc9efa-96e9-4d85-8747-89fcc4b66db6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=617367701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.617367701
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4219622534
Short name T918
Test name
Test status
Simulation time 49099833 ps
CPU time 1.28 seconds
Started Jun 02 01:41:46 PM PDT 24
Finished Jun 02 01:41:48 PM PDT 24
Peak memory 196988 kb
Host smart-489c4012-928e-4b33-91ed-150dcd81624e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219622534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4219622534
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3850140235
Short name T893
Test name
Test status
Simulation time 69551198 ps
CPU time 1.01 seconds
Started Jun 02 01:41:59 PM PDT 24
Finished Jun 02 01:42:00 PM PDT 24
Peak memory 196824 kb
Host smart-cd70afed-07fa-4ac8-a3e7-d876f84d686c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3850140235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3850140235
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3496021418
Short name T875
Test name
Test status
Simulation time 319451169 ps
CPU time 1.49 seconds
Started Jun 02 01:41:58 PM PDT 24
Finished Jun 02 01:42:00 PM PDT 24
Peak memory 197008 kb
Host smart-e1adf00f-82bf-4f1f-9b44-aa2a0278f43d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496021418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3496021418
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2745670494
Short name T919
Test name
Test status
Simulation time 309446065 ps
CPU time 1.29 seconds
Started Jun 02 01:41:58 PM PDT 24
Finished Jun 02 01:42:00 PM PDT 24
Peak memory 197000 kb
Host smart-8da81f15-dc60-4a86-931a-974e7a0262c2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2745670494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2745670494
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2373801390
Short name T889
Test name
Test status
Simulation time 147506690 ps
CPU time 1.29 seconds
Started Jun 02 01:41:57 PM PDT 24
Finished Jun 02 01:41:58 PM PDT 24
Peak memory 196824 kb
Host smart-c6d73301-e5e0-496e-86a1-dc76192c5a7b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373801390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2373801390
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.268130733
Short name T905
Test name
Test status
Simulation time 246041704 ps
CPU time 0.79 seconds
Started Jun 02 01:41:57 PM PDT 24
Finished Jun 02 01:41:58 PM PDT 24
Peak memory 195696 kb
Host smart-f5ac3efb-d3f6-4bbe-acb7-af40e14902bc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=268130733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.268130733
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4023506147
Short name T933
Test name
Test status
Simulation time 80015250 ps
CPU time 1.58 seconds
Started Jun 02 01:42:05 PM PDT 24
Finished Jun 02 01:42:07 PM PDT 24
Peak memory 196920 kb
Host smart-14a889a2-849c-4cc4-9f2f-1fc3058286a9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023506147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4023506147
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2744699474
Short name T888
Test name
Test status
Simulation time 81726643 ps
CPU time 0.89 seconds
Started Jun 02 01:42:04 PM PDT 24
Finished Jun 02 01:42:06 PM PDT 24
Peak memory 196428 kb
Host smart-60b6258b-4f73-4bf1-b08e-f5d70ed85e09
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2744699474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2744699474
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1576794276
Short name T920
Test name
Test status
Simulation time 69111883 ps
CPU time 1.31 seconds
Started Jun 02 01:42:04 PM PDT 24
Finished Jun 02 01:42:05 PM PDT 24
Peak memory 198432 kb
Host smart-a8dd3d37-4cdd-4206-b2ea-47fa861f2d57
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576794276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1576794276
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.735316606
Short name T930
Test name
Test status
Simulation time 74401564 ps
CPU time 1.27 seconds
Started Jun 02 01:42:05 PM PDT 24
Finished Jun 02 01:42:07 PM PDT 24
Peak memory 197016 kb
Host smart-9abda1ed-dd10-4832-80cb-c4a2ad67702f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=735316606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.735316606
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2106594943
Short name T909
Test name
Test status
Simulation time 37703074 ps
CPU time 0.74 seconds
Started Jun 02 01:42:06 PM PDT 24
Finished Jun 02 01:42:07 PM PDT 24
Peak memory 194648 kb
Host smart-20417283-0d84-49c7-bff9-9d1204154a3b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106594943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2106594943
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.430658684
Short name T937
Test name
Test status
Simulation time 140853710 ps
CPU time 1 seconds
Started Jun 02 01:42:02 PM PDT 24
Finished Jun 02 01:42:04 PM PDT 24
Peak memory 196656 kb
Host smart-cbf41095-fab1-4ca1-be5b-3c1d2b9f5188
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=430658684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.430658684
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3498747267
Short name T867
Test name
Test status
Simulation time 94740790 ps
CPU time 1.43 seconds
Started Jun 02 01:42:03 PM PDT 24
Finished Jun 02 01:42:05 PM PDT 24
Peak memory 197080 kb
Host smart-d376b552-a9c8-47f6-bf2b-f8baa2f9a0d8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498747267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3498747267
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3004775173
Short name T932
Test name
Test status
Simulation time 122864436 ps
CPU time 1.04 seconds
Started Jun 02 01:42:04 PM PDT 24
Finished Jun 02 01:42:05 PM PDT 24
Peak memory 196692 kb
Host smart-6669c0eb-9482-44f8-a98d-a04c6c15d56a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3004775173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3004775173
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4058393086
Short name T921
Test name
Test status
Simulation time 46424607 ps
CPU time 1.28 seconds
Started Jun 02 01:42:05 PM PDT 24
Finished Jun 02 01:42:07 PM PDT 24
Peak memory 196648 kb
Host smart-6f1c5b74-5589-4cfa-b331-13a1e02312e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058393086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4058393086
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3386826096
Short name T924
Test name
Test status
Simulation time 43927905 ps
CPU time 1.21 seconds
Started Jun 02 01:42:02 PM PDT 24
Finished Jun 02 01:42:03 PM PDT 24
Peak memory 196972 kb
Host smart-e572a3a8-9065-4fed-9b87-e0642970d197
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3386826096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3386826096
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2224764207
Short name T917
Test name
Test status
Simulation time 154586716 ps
CPU time 1.26 seconds
Started Jun 02 01:42:04 PM PDT 24
Finished Jun 02 01:42:05 PM PDT 24
Peak memory 196788 kb
Host smart-4518c5e6-f1cf-43da-a43d-17cf40057092
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224764207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2224764207
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1657627682
Short name T883
Test name
Test status
Simulation time 96547792 ps
CPU time 1.28 seconds
Started Jun 02 01:42:05 PM PDT 24
Finished Jun 02 01:42:07 PM PDT 24
Peak memory 195888 kb
Host smart-805ca7ba-c3b3-4499-8dcb-1156d1070c23
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1657627682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1657627682
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3143919059
Short name T891
Test name
Test status
Simulation time 97080662 ps
CPU time 0.89 seconds
Started Jun 02 01:42:03 PM PDT 24
Finished Jun 02 01:42:05 PM PDT 24
Peak memory 198088 kb
Host smart-aef50e2d-efce-442f-9311-795cd47c6d88
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143919059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3143919059
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3905469467
Short name T853
Test name
Test status
Simulation time 44931203 ps
CPU time 0.99 seconds
Started Jun 02 01:42:04 PM PDT 24
Finished Jun 02 01:42:05 PM PDT 24
Peak memory 196584 kb
Host smart-f61d5802-50de-4caa-a415-9e771a6a195a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3905469467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3905469467
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.422927517
Short name T876
Test name
Test status
Simulation time 112035715 ps
CPU time 1.19 seconds
Started Jun 02 01:42:03 PM PDT 24
Finished Jun 02 01:42:05 PM PDT 24
Peak memory 196096 kb
Host smart-8e32384f-765c-4810-bd4d-189e349a58a1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422927517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.422927517
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1180257604
Short name T935
Test name
Test status
Simulation time 49364589 ps
CPU time 0.95 seconds
Started Jun 02 01:41:47 PM PDT 24
Finished Jun 02 01:41:49 PM PDT 24
Peak memory 196716 kb
Host smart-acf43cf9-4c9e-4088-bf7f-451c5a811867
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1180257604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1180257604
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1690895641
Short name T877
Test name
Test status
Simulation time 139271427 ps
CPU time 1.15 seconds
Started Jun 02 01:41:46 PM PDT 24
Finished Jun 02 01:41:48 PM PDT 24
Peak memory 196964 kb
Host smart-1c96c175-6591-49f8-aab3-ec2325ea4e32
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690895641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1690895641
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.842045814
Short name T852
Test name
Test status
Simulation time 43222602 ps
CPU time 1.33 seconds
Started Jun 02 01:42:05 PM PDT 24
Finished Jun 02 01:42:07 PM PDT 24
Peak memory 198196 kb
Host smart-8dd26613-09bb-4644-ad40-f95a5e7df7b6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=842045814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.842045814
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1692162051
Short name T884
Test name
Test status
Simulation time 206444441 ps
CPU time 1.13 seconds
Started Jun 02 01:42:03 PM PDT 24
Finished Jun 02 01:42:04 PM PDT 24
Peak memory 196944 kb
Host smart-dea36822-3ef5-4f40-9efd-19a85f40853f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692162051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1692162051
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1706005300
Short name T936
Test name
Test status
Simulation time 230901112 ps
CPU time 1.23 seconds
Started Jun 02 01:42:05 PM PDT 24
Finished Jun 02 01:42:07 PM PDT 24
Peak memory 196692 kb
Host smart-9ef10aa5-90cd-4dff-b418-43ca2b908f59
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1706005300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1706005300
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3075989895
Short name T912
Test name
Test status
Simulation time 75998904 ps
CPU time 1.23 seconds
Started Jun 02 01:42:03 PM PDT 24
Finished Jun 02 01:42:04 PM PDT 24
Peak memory 196888 kb
Host smart-1495bd74-7a27-42fb-9a8e-8722ec817c15
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075989895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3075989895
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3109604101
Short name T858
Test name
Test status
Simulation time 274812461 ps
CPU time 1.22 seconds
Started Jun 02 01:42:02 PM PDT 24
Finished Jun 02 01:42:04 PM PDT 24
Peak memory 196764 kb
Host smart-2bd24cf9-d01e-41ac-819e-0062b8815b85
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3109604101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3109604101
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3473308969
Short name T894
Test name
Test status
Simulation time 27658423 ps
CPU time 0.67 seconds
Started Jun 02 01:42:03 PM PDT 24
Finished Jun 02 01:42:05 PM PDT 24
Peak memory 194512 kb
Host smart-01de0913-80fc-4a4b-bffd-55081769c85b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473308969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3473308969
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.11468009
Short name T844
Test name
Test status
Simulation time 53746362 ps
CPU time 1.13 seconds
Started Jun 02 01:42:10 PM PDT 24
Finished Jun 02 01:42:11 PM PDT 24
Peak memory 197816 kb
Host smart-da88c519-1113-4e0f-a537-33f1145e3859
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=11468009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.11468009
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4132090058
Short name T931
Test name
Test status
Simulation time 304413504 ps
CPU time 1.48 seconds
Started Jun 02 01:42:09 PM PDT 24
Finished Jun 02 01:42:11 PM PDT 24
Peak memory 196892 kb
Host smart-679d4bc9-44ba-4bb6-8913-033d9640ce8a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132090058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4132090058
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1967220636
Short name T897
Test name
Test status
Simulation time 127087612 ps
CPU time 0.98 seconds
Started Jun 02 01:42:09 PM PDT 24
Finished Jun 02 01:42:11 PM PDT 24
Peak memory 198112 kb
Host smart-795f5597-1655-4b2a-a1ab-7784b8ad4dd3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1967220636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1967220636
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2718466261
Short name T913
Test name
Test status
Simulation time 202214040 ps
CPU time 1.27 seconds
Started Jun 02 01:42:09 PM PDT 24
Finished Jun 02 01:42:11 PM PDT 24
Peak memory 196400 kb
Host smart-112ae47e-b54c-4914-9f4b-5073c3585b49
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718466261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2718466261
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1876700506
Short name T907
Test name
Test status
Simulation time 272839964 ps
CPU time 0.72 seconds
Started Jun 02 01:42:09 PM PDT 24
Finished Jun 02 01:42:11 PM PDT 24
Peak memory 195320 kb
Host smart-fbd0803d-3d67-461a-9988-c43e20c66f01
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1876700506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1876700506
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4019231561
Short name T941
Test name
Test status
Simulation time 55601649 ps
CPU time 1.31 seconds
Started Jun 02 01:42:09 PM PDT 24
Finished Jun 02 01:42:11 PM PDT 24
Peak memory 198172 kb
Host smart-b746531b-ee4f-4cdb-a459-116fb42ea4f0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019231561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4019231561
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2358169734
Short name T885
Test name
Test status
Simulation time 79732944 ps
CPU time 1.19 seconds
Started Jun 02 01:42:10 PM PDT 24
Finished Jun 02 01:42:12 PM PDT 24
Peak memory 196684 kb
Host smart-54ad42ea-aa9c-48e1-8d07-7918c7269c36
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2358169734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2358169734
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4246870590
Short name T880
Test name
Test status
Simulation time 164940181 ps
CPU time 0.94 seconds
Started Jun 02 01:42:11 PM PDT 24
Finished Jun 02 01:42:12 PM PDT 24
Peak memory 195804 kb
Host smart-6911fed9-5b63-4b59-bee2-91038ed671c4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246870590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4246870590
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.126478379
Short name T861
Test name
Test status
Simulation time 127387190 ps
CPU time 1.21 seconds
Started Jun 02 01:42:11 PM PDT 24
Finished Jun 02 01:42:13 PM PDT 24
Peak memory 196672 kb
Host smart-0878f21b-84e6-40ea-9c4a-78aa55e2ec0b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=126478379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.126478379
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.862111718
Short name T882
Test name
Test status
Simulation time 42596830 ps
CPU time 0.86 seconds
Started Jun 02 01:42:09 PM PDT 24
Finished Jun 02 01:42:11 PM PDT 24
Peak memory 196820 kb
Host smart-1111b514-21d5-47d0-9691-a5b272afc83c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862111718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.862111718
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.354560098
Short name T914
Test name
Test status
Simulation time 74590185 ps
CPU time 1.21 seconds
Started Jun 02 01:42:10 PM PDT 24
Finished Jun 02 01:42:12 PM PDT 24
Peak memory 196896 kb
Host smart-6a72b340-dbf3-44a2-9529-136ff94953fd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=354560098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.354560098
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.267478412
Short name T903
Test name
Test status
Simulation time 26298880 ps
CPU time 0.78 seconds
Started Jun 02 01:42:10 PM PDT 24
Finished Jun 02 01:42:11 PM PDT 24
Peak memory 194568 kb
Host smart-37fa7c1e-f614-4699-becc-284207cc7482
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267478412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.267478412
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.772872122
Short name T886
Test name
Test status
Simulation time 168994420 ps
CPU time 1.35 seconds
Started Jun 02 01:42:09 PM PDT 24
Finished Jun 02 01:42:11 PM PDT 24
Peak memory 196668 kb
Host smart-40aae6a9-6b22-4506-ba7b-917ea5b46607
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=772872122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.772872122
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3173317797
Short name T892
Test name
Test status
Simulation time 26431077 ps
CPU time 0.86 seconds
Started Jun 02 01:42:17 PM PDT 24
Finished Jun 02 01:42:19 PM PDT 24
Peak memory 196232 kb
Host smart-d1976fdd-cab1-4c40-b971-1000ecc082c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173317797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3173317797
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2320765137
Short name T923
Test name
Test status
Simulation time 44709247 ps
CPU time 1.04 seconds
Started Jun 02 01:41:49 PM PDT 24
Finished Jun 02 01:41:51 PM PDT 24
Peak memory 198144 kb
Host smart-c49f91bf-5adc-4629-9c9a-2f093449fdca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2320765137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2320765137
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2858926821
Short name T927
Test name
Test status
Simulation time 374392338 ps
CPU time 1.26 seconds
Started Jun 02 01:41:46 PM PDT 24
Finished Jun 02 01:41:48 PM PDT 24
Peak memory 196744 kb
Host smart-2ee98452-a897-4c7f-80c9-c1f90aef3082
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858926821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2858926821
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.840902695
Short name T934
Test name
Test status
Simulation time 91153377 ps
CPU time 0.96 seconds
Started Jun 02 01:41:46 PM PDT 24
Finished Jun 02 01:41:48 PM PDT 24
Peak memory 196664 kb
Host smart-6db5aec1-d947-4e13-a001-3f182f171acb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=840902695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.840902695
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3366968950
Short name T942
Test name
Test status
Simulation time 80990419 ps
CPU time 0.97 seconds
Started Jun 02 01:41:47 PM PDT 24
Finished Jun 02 01:41:49 PM PDT 24
Peak memory 196816 kb
Host smart-a30118d1-329e-41fc-9d76-f6cb6edb55bb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366968950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3366968950
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1583412879
Short name T911
Test name
Test status
Simulation time 85378552 ps
CPU time 1.21 seconds
Started Jun 02 01:41:51 PM PDT 24
Finished Jun 02 01:41:53 PM PDT 24
Peak memory 196804 kb
Host smart-20b1eab0-2234-4138-ad52-02c36700835b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1583412879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1583412879
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2092952367
Short name T915
Test name
Test status
Simulation time 47531748 ps
CPU time 1.12 seconds
Started Jun 02 01:41:48 PM PDT 24
Finished Jun 02 01:41:50 PM PDT 24
Peak memory 198156 kb
Host smart-fdcf8b0c-1003-48cf-9ea6-13b19d81c6fc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092952367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2092952367
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.4018204094
Short name T855
Test name
Test status
Simulation time 70605891 ps
CPU time 1.1 seconds
Started Jun 02 01:41:46 PM PDT 24
Finished Jun 02 01:41:48 PM PDT 24
Peak memory 196040 kb
Host smart-0b4dadc2-bdb4-4923-9e8d-147d25ef7ba1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4018204094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.4018204094
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3199529302
Short name T866
Test name
Test status
Simulation time 159773886 ps
CPU time 1.25 seconds
Started Jun 02 01:41:51 PM PDT 24
Finished Jun 02 01:41:53 PM PDT 24
Peak memory 196848 kb
Host smart-4c20f765-9233-4242-8f8e-2e7af9398a65
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199529302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3199529302
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2623740314
Short name T859
Test name
Test status
Simulation time 342513675 ps
CPU time 1.45 seconds
Started Jun 02 01:41:46 PM PDT 24
Finished Jun 02 01:41:48 PM PDT 24
Peak memory 196820 kb
Host smart-67740b33-d7b9-41f2-b0db-5e3620a9320d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2623740314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2623740314
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.213619737
Short name T879
Test name
Test status
Simulation time 59786103 ps
CPU time 1.07 seconds
Started Jun 02 01:41:45 PM PDT 24
Finished Jun 02 01:41:47 PM PDT 24
Peak memory 196032 kb
Host smart-0abd69d0-747e-4196-82d0-71dec2ecd164
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213619737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.213619737
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%