Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4144177	1			T22	22852		T23	65		T24	81
all_pins[1]	4144177	1			T22	22852		T23	65		T24	81
all_pins[2]	4144177	1			T22	22852		T23	65		T24	81
all_pins[3]	4144177	1			T22	22852		T23	65		T24	81
all_pins[4]	4144177	1			T22	22852		T23	65		T24	81
all_pins[5]	4144177	1			T22	22852		T23	65		T24	81
all_pins[6]	4144177	1			T22	22852		T23	65		T24	81
all_pins[7]	4144177	1			T22	22852		T23	65		T24	81
all_pins[8]	4144177	1			T22	22852		T23	65		T24	81
all_pins[9]	4144177	1			T22	22852		T23	65		T24	81
all_pins[10]	4144177	1			T22	22852		T23	65		T24	81
all_pins[11]	4144177	1			T22	22852		T23	65		T24	81
all_pins[12]	4144177	1			T22	22852		T23	65		T24	81
all_pins[13]	4144177	1			T22	22852		T23	65		T24	81
all_pins[14]	4144177	1			T22	22852		T23	65		T24	81
all_pins[15]	4144177	1			T22	22852		T23	65		T24	81
all_pins[16]	4144177	1			T22	22852		T23	65		T24	81
all_pins[17]	4144177	1			T22	22852		T23	65		T24	81
all_pins[18]	4144177	1			T22	22852		T23	65		T24	81
all_pins[19]	4144177	1			T22	22852		T23	65		T24	81
all_pins[20]	4144177	1			T22	22852		T23	65		T24	81
all_pins[21]	4144177	1			T22	22852		T23	65		T24	81
all_pins[22]	4144177	1			T22	22852		T23	65		T24	81
all_pins[23]	4144177	1			T22	22852		T23	65		T24	81
all_pins[24]	4144177	1			T22	22852		T23	65		T24	81
all_pins[25]	4144177	1			T22	22852		T23	65		T24	81
all_pins[26]	4144177	1			T22	22852		T23	65		T24	81
all_pins[27]	4144177	1			T22	22852		T23	65		T24	81
all_pins[28]	4144177	1			T22	22852		T23	65		T24	81
all_pins[29]	4144177	1			T22	22852		T23	65		T24	81
all_pins[30]	4144177	1			T22	22852		T23	65		T24	81
all_pins[31]	4144177	1			T22	22852		T23	65		T24	81

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	82377221	1			T22	454588		T23	1079		T24	1329
values[0x1]	50236443	1			T22	276676		T23	1001		T24	1263
transitions[0x0=>0x1]	30109369	1			T22	165749		T23	509		T24	636
transitions[0x1=>0x0]	30109231	1			T22	165749		T23	508		T24	635

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2572638	1			T22	14359		T23	37		T24	42
all_pins[0]	values[0x1]	1571539	1			T22	8493		T23	28		T24	39
all_pins[0]	transitions[0x0=>0x1]	974390	1			T22	5217		T23	11		T24	20
all_pins[0]	transitions[0x1=>0x0]	970448	1			T22	5378		T23	19		T24	16
all_pins[1]	values[0x0]	2571962	1			T22	14602		T23	32		T24	46
all_pins[1]	values[0x1]	1572215	1			T22	8250		T23	33		T24	35
all_pins[1]	transitions[0x0=>0x1]	939524	1			T22	5013		T23	16		T24	19
all_pins[1]	transitions[0x1=>0x0]	938848	1			T22	5256		T23	11		T24	23
all_pins[2]	values[0x0]	2574708	1			T22	14167		T23	39		T24	49
all_pins[2]	values[0x1]	1569469	1			T22	8685		T23	26		T24	32
all_pins[2]	transitions[0x0=>0x1]	937590	1			T22	5457		T23	11		T24	16
all_pins[2]	transitions[0x1=>0x0]	940336	1			T22	5022		T23	18		T24	19
all_pins[3]	values[0x0]	2573244	1			T22	14342		T23	36		T24	48
all_pins[3]	values[0x1]	1570933	1			T22	8510		T23	29		T24	33
all_pins[3]	transitions[0x0=>0x1]	937817	1			T22	5049		T23	17		T24	22
all_pins[3]	transitions[0x1=>0x0]	936353	1			T22	5224		T23	14		T24	21
all_pins[4]	values[0x0]	2574586	1			T22	14053		T23	27		T24	40
all_pins[4]	values[0x1]	1569591	1			T22	8799		T23	38		T24	41
all_pins[4]	transitions[0x0=>0x1]	941074	1			T22	5462		T23	22		T24	24
all_pins[4]	transitions[0x1=>0x0]	942416	1			T22	5173		T23	13		T24	16
all_pins[5]	values[0x0]	2572730	1			T22	14160		T23	23		T24	45
all_pins[5]	values[0x1]	1571447	1			T22	8692		T23	42		T24	36
all_pins[5]	transitions[0x0=>0x1]	942305	1			T22	5128		T23	17		T24	19
all_pins[5]	transitions[0x1=>0x0]	940449	1			T22	5235		T23	13		T24	24
all_pins[6]	values[0x0]	2571757	1			T22	14325		T23	30		T24	44
all_pins[6]	values[0x1]	1572420	1			T22	8527		T23	35		T24	37
all_pins[6]	transitions[0x0=>0x1]	940354	1			T22	5127		T23	11		T24	21
all_pins[6]	transitions[0x1=>0x0]	939381	1			T22	5292		T23	18		T24	20
all_pins[7]	values[0x0]	2571355	1			T22	14187		T23	35		T24	41
all_pins[7]	values[0x1]	1572822	1			T22	8665		T23	30		T24	40
all_pins[7]	transitions[0x0=>0x1]	940974	1			T22	5007		T23	12		T24	19
all_pins[7]	transitions[0x1=>0x0]	940572	1			T22	4869		T23	17		T24	16
all_pins[8]	values[0x0]	2577933	1			T22	14317		T23	33		T24	43
all_pins[8]	values[0x1]	1566244	1			T22	8535		T23	32		T24	38
all_pins[8]	transitions[0x0=>0x1]	935423	1			T22	5202		T23	16		T24	18
all_pins[8]	transitions[0x1=>0x0]	942001	1			T22	5332		T23	14		T24	20
all_pins[9]	values[0x0]	2577963	1			T22	13787		T23	35		T24	45
all_pins[9]	values[0x1]	1566214	1			T22	9065		T23	30		T24	36
all_pins[9]	transitions[0x0=>0x1]	939893	1			T22	5385		T23	16		T24	17
all_pins[9]	transitions[0x1=>0x0]	939923	1			T22	4855		T23	18		T24	19
all_pins[10]	values[0x0]	2576702	1			T22	14702		T23	46		T24	39
all_pins[10]	values[0x1]	1567475	1			T22	8150		T23	19		T24	42
all_pins[10]	transitions[0x0=>0x1]	939221	1			T22	4585		T23	12		T24	28
all_pins[10]	transitions[0x1=>0x0]	937960	1			T22	5500		T23	23		T24	22
all_pins[11]	values[0x0]	2574161	1			T22	14036		T23	34		T24	35
all_pins[11]	values[0x1]	1570016	1			T22	8816		T23	31		T24	46
all_pins[11]	transitions[0x0=>0x1]	941189	1			T22	5443		T23	21		T24	20
all_pins[11]	transitions[0x1=>0x0]	938648	1			T22	4777		T23	9		T24	16
all_pins[12]	values[0x0]	2576560	1			T22	13884		T23	39		T24	50
all_pins[12]	values[0x1]	1567617	1			T22	8968		T23	26		T24	31
all_pins[12]	transitions[0x0=>0x1]	940911	1			T22	5288		T23	13		T24	14
all_pins[12]	transitions[0x1=>0x0]	943310	1			T22	5136		T23	18		T24	29
all_pins[13]	values[0x0]	2577963	1			T22	14493		T23	33		T24	36
all_pins[13]	values[0x1]	1566214	1			T22	8359		T23	32		T24	45
all_pins[13]	transitions[0x0=>0x1]	939856	1			T22	4845		T23	18		T24	26
all_pins[13]	transitions[0x1=>0x0]	941259	1			T22	5454		T23	12		T24	12
all_pins[14]	values[0x0]	2570288	1			T22	14005		T23	30		T24	35
all_pins[14]	values[0x1]	1573889	1			T22	8847		T23	35		T24	46
all_pins[14]	transitions[0x0=>0x1]	942693	1			T22	5256		T23	19		T24	18
all_pins[14]	transitions[0x1=>0x0]	935018	1			T22	4768		T23	16		T24	17
all_pins[15]	values[0x0]	2568766	1			T22	14253		T23	27		T24	42
all_pins[15]	values[0x1]	1575411	1			T22	8599		T23	38		T24	39
all_pins[15]	transitions[0x0=>0x1]	941241	1			T22	5116		T23	16		T24	20
all_pins[15]	transitions[0x1=>0x0]	939719	1			T22	5364		T23	13		T24	27
all_pins[16]	values[0x0]	2574152	1			T22	14279		T23	35		T24	40
all_pins[16]	values[0x1]	1570025	1			T22	8573		T23	30		T24	41
all_pins[16]	transitions[0x0=>0x1]	938977	1			T22	5189		T23	14		T24	21
all_pins[16]	transitions[0x1=>0x0]	944363	1			T22	5215		T23	22		T24	19
all_pins[17]	values[0x0]	2570392	1			T22	14114		T23	29		T24	47
all_pins[17]	values[0x1]	1573785	1			T22	8738		T23	36		T24	34
all_pins[17]	transitions[0x0=>0x1]	942064	1			T22	5127		T23	20		T24	17
all_pins[17]	transitions[0x1=>0x0]	938304	1			T22	4962		T23	14		T24	24
all_pins[18]	values[0x0]	2568630	1			T22	14569		T23	36		T24	49
all_pins[18]	values[0x1]	1575547	1			T22	8283		T23	29		T24	32
all_pins[18]	transitions[0x0=>0x1]	938307	1			T22	5033		T23	10		T24	15
all_pins[18]	transitions[0x1=>0x0]	936545	1			T22	5488		T23	17		T24	17
all_pins[19]	values[0x0]	2575855	1			T22	14332		T23	37		T24	37
all_pins[19]	values[0x1]	1568322	1			T22	8520		T23	28		T24	44
all_pins[19]	transitions[0x0=>0x1]	938423	1			T22	5399		T23	14		T24	27
all_pins[19]	transitions[0x1=>0x0]	945648	1			T22	5162		T23	15		T24	15
all_pins[20]	values[0x0]	2572868	1			T22	14506		T23	36		T24	42
all_pins[20]	values[0x1]	1571309	1			T22	8346		T23	29		T24	39
all_pins[20]	transitions[0x0=>0x1]	943065	1			T22	5020		T23	17		T24	20
all_pins[20]	transitions[0x1=>0x0]	940078	1			T22	5194		T23	16		T24	25
all_pins[21]	values[0x0]	2575774	1			T22	14616		T23	34		T24	45
all_pins[21]	values[0x1]	1568403	1			T22	8236		T23	31		T24	36
all_pins[21]	transitions[0x0=>0x1]	937967	1			T22	5055		T23	14		T24	17
all_pins[21]	transitions[0x1=>0x0]	940873	1			T22	5165		T23	12		T24	20
all_pins[22]	values[0x0]	2582114	1			T22	14010		T23	26		T24	40
all_pins[22]	values[0x1]	1562063	1			T22	8842		T23	39		T24	41
all_pins[22]	transitions[0x0=>0x1]	935377	1			T22	5470		T23	22		T24	24
all_pins[22]	transitions[0x1=>0x0]	941717	1			T22	4864		T23	14		T24	19
all_pins[23]	values[0x0]	2572470	1			T22	14092		T23	27		T24	45
all_pins[23]	values[0x1]	1571707	1			T22	8760		T23	38		T24	36
all_pins[23]	transitions[0x0=>0x1]	944659	1			T22	5148		T23	13		T24	17
all_pins[23]	transitions[0x1=>0x0]	935015	1			T22	5230		T23	14		T24	22
all_pins[24]	values[0x0]	2573586	1			T22	13817		T23	26		T24	39
all_pins[24]	values[0x1]	1570591	1			T22	9035		T23	39		T24	42
all_pins[24]	transitions[0x0=>0x1]	937427	1			T22	5328		T23	18		T24	19
all_pins[24]	transitions[0x1=>0x0]	938543	1			T22	5053		T23	17		T24	13
all_pins[25]	values[0x0]	2572288	1			T22	14201		T23	42		T24	35
all_pins[25]	values[0x1]	1571889	1			T22	8651		T23	23		T24	46
all_pins[25]	transitions[0x0=>0x1]	942268	1			T22	4914		T23	13		T24	27
all_pins[25]	transitions[0x1=>0x0]	940970	1			T22	5298		T23	29		T24	23
all_pins[26]	values[0x0]	2575315	1			T22	13732		T23	40		T24	40
all_pins[26]	values[0x1]	1568862	1			T22	9120		T23	25		T24	41
all_pins[26]	transitions[0x0=>0x1]	938343	1			T22	5508		T23	13		T24	18
all_pins[26]	transitions[0x1=>0x0]	941370	1			T22	5039		T23	11		T24	23
all_pins[27]	values[0x0]	2576527	1			T22	14438		T23	40		T24	34
all_pins[27]	values[0x1]	1567650	1			T22	8414		T23	25		T24	47
all_pins[27]	transitions[0x0=>0x1]	939046	1			T22	4888		T23	16		T24	27
all_pins[27]	transitions[0x1=>0x0]	940258	1			T22	5594		T23	16		T24	21
all_pins[28]	values[0x0]	2573257	1			T22	14279		T23	37		T24	31
all_pins[28]	values[0x1]	1570920	1			T22	8573		T23	28		T24	50
all_pins[28]	transitions[0x0=>0x1]	940971	1			T22	5137		T23	19		T24	18
all_pins[28]	transitions[0x1=>0x0]	937701	1			T22	4978		T23	16		T24	15
all_pins[29]	values[0x0]	2574889	1			T22	13721		T23	32		T24	37
all_pins[29]	values[0x1]	1569288	1			T22	9131		T23	33		T24	44
all_pins[29]	transitions[0x0=>0x1]	938633	1			T22	5590		T23	19		T24	15
all_pins[29]	transitions[0x1=>0x0]	940265	1			T22	5032		T23	14		T24	21
all_pins[30]	values[0x0]	2579346	1			T22	14012		T23	38		T24	43
all_pins[30]	values[0x1]	1564831	1			T22	8840		T23	27		T24	38
all_pins[30]	transitions[0x0=>0x1]	936158	1			T22	5107		T23	16		T24	16
all_pins[30]	transitions[0x1=>0x0]	940615	1			T22	5398		T23	22		T24	22
all_pins[31]	values[0x0]	2576442	1			T22	14198		T23	28		T24	45
all_pins[31]	values[0x1]	1567735	1			T22	8654		T23	37		T24	36
all_pins[31]	transitions[0x0=>0x1]	943229	1			T22	5256		T23	23		T24	17
all_pins[31]	transitions[0x1=>0x0]	940325	1			T22	5442		T23	13		T24	19