Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[1]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[2]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[3]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[4]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[5]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[6]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[7]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[8]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[9]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[10]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[11]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[12]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[13]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[14]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[15]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[16]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[17]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[18]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[19]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[20]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[21]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[22]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[23]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[24]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[25]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[26]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[27]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[28]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[29]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[30]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[31]	13474539	1			T22	65388		T23	930		T24	1336

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

252253253

1

T22

730609

T23

14916

T24

20976

auto[1]

178931995

1

T22

136180

T23

14844

T24

21776

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

345208632

1

T22

164638

T23

29760

T24

42752

auto[1]

85976616

1

T22

446031

T25

3968

T28

2110

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

320205648

1

T22

151327

T23

29760

T24

42752

auto[1]

110979600

1

T22

579137

T25

8917

T28

2292

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4893298	1			T22	15033		T23	497		T24	665
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3756789	1			T22	24908		T23	433		T24	671
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1352564	1			T22	7238		T25	66		T28	40
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1626890	1			T22	806		T25	177		T28	39
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	500570	1			T22	10573		T25	36		T30	12
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1344428	1			T22	6830		T25	53		T28	28
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4900359	1			T22	14929		T23	421		T24	786
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3751986	1			T22	25214		T23	509		T24	550
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1353612	1			T22	7000		T25	109		T28	30
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1625719	1			T22	695		T25	102		T28	29
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	502678	1			T22	10386		T25	22		T30	32
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1340185	1			T22	7164		T25	28		T28	46
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4902730	1			T22	15149		T23	481		T24	672
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3753356	1			T22	25420		T23	449		T24	664
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1356200	1			T22	7253		T25	32		T28	42
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1621553	1			T22	676		T25	162		T28	34
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	502517	1			T22	10086		T25	48		T30	26
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1338183	1			T22	6804		T25	79		T28	38
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4902842	1			T22	15025		T23	476		T24	753
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3752608	1			T22	24976		T23	454		T24	583
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1351988	1			T22	6987		T25	64		T28	32
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1625000	1			T22	722		T25	179		T28	24
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	503961	1			T22	10453		T25	31		T30	14
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1338140	1			T22	7225		T25	82		T28	40
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4891849	1			T22	15240		T23	371		T24	649
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3751187	1			T22	25048		T23	559		T24	687
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1346877	1			T22	6865		T25	47		T28	33
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1629608	1			T22	737		T25	168		T28	32
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	503626	1			T22	10493		T25	27		T30	16
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1351392	1			T22	7005		T25	42		T28	40
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4909936	1			T22	14935		T23	429		T24	722
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3748840	1			T22	25139		T23	501		T24	614
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1352282	1			T22	6796		T25	52		T28	38
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1622741	1			T22	816		T25	169		T28	40
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	503032	1			T22	10918		T25	18		T30	10
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1337708	1			T22	6784		T25	54		T28	43
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4913590	1			T22	14930		T23	416		T24	650
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3745423	1			T22	24734		T23	514		T24	686
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1349329	1			T22	6530		T25	62		T28	24
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1626379	1			T22	896		T25	140		T28	40
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	501896	1			T22	11052		T25	12		T30	16
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1337922	1			T22	7246		T25	68		T28	40
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4915436	1			T22	15188		T23	433		T24	642
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3743464	1			T22	25030		T23	497		T24	694
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1353566	1			T22	7144		T25	73		T28	32
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1621222	1			T22	720		T25	165		T28	31
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	503594	1			T22	10391		T25	32		T30	31
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1337257	1			T22	6915		T25	62		T28	52
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4902077	1			T22	15163		T23	484		T24	624
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3754713	1			T22	25171		T23	446		T24	712
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1353220	1			T22	7067		T25	81		T28	17
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1625331	1			T22	710		T25	187		T28	36
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	500915	1			T22	10504		T25	28		T30	31
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1338283	1			T22	6773		T25	67		T28	44
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4903859	1			T22	15228		T23	458		T24	640
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3750869	1			T22	25220		T23	472		T24	696
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1352875	1			T22	7082		T25	61		T28	32
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1621664	1			T22	772		T25	174		T28	31
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	503330	1			T22	10483		T25	35		T30	31
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1341942	1			T22	6603		T25	63		T28	40
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4891608	1			T22	15126		T23	460		T24	752
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3760316	1			T22	25001		T23	470		T24	584
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1353595	1			T22	6953		T25	48		T28	27
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1626011	1			T22	813		T25	189		T28	34
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	505745	1			T22	10714		T25	32		T30	21
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1337264	1			T22	6781		T25	101		T28	22
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4910479	1			T22	15068		T23	418		T24	661
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3744871	1			T22	25139		T23	512		T24	675
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1351208	1			T22	6755		T25	71		T28	26
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1629946	1			T22	732		T25	217		T28	44
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	504949	1			T22	10586		T25	33		T30	12
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1333086	1			T22	7108		T25	75		T28	31
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4906146	1			T22	15200		T23	534		T24	621
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3752185	1			T22	25190		T23	396		T24	715
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1348669	1			T22	7129		T25	36		T28	34
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1624305	1			T22	695		T25	245		T28	29
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	504254	1			T22	10428		T25	28		T30	24
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1338980	1			T22	6746		T25	86		T28	38
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4900494	1			T22	15281		T23	550		T24	671
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3744363	1			T22	25085		T23	380		T24	665
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1348941	1			T22	6788		T25	86		T28	16
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1629761	1			T22	752		T25	179		T28	52
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	505204	1			T22	10359		T25	26		T30	17
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1345776	1			T22	7123		T25	90		T28	20
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4903570	1			T22	14970		T23	510		T24	678
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3750716	1			T22	25260		T23	420		T24	658
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1350222	1			T22	6649		T25	58		T28	20
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1621593	1			T22	700		T25	184		T28	42
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	501290	1			T22	10939		T25	37		T30	19
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1347148	1			T22	6870		T25	73		T28	49
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4897257	1			T22	15028		T23	461		T24	584
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3751332	1			T22	25446		T23	469		T24	752
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1349894	1			T22	7339		T25	52		T28	30
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1632553	1			T22	763		T25	170		T28	34
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	503702	1			T22	10315		T25	39		T30	16
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1339801	1			T22	6497		T25	96		T28	30
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4902682	1			T22	15038		T23	376		T24	740
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3756418	1			T22	25211		T23	554		T24	596
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1345574	1			T22	7162		T25	56		T28	40
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1634227	1			T22	704		T25	209		T28	27
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	504358	1			T22	10335		T25	38		T30	16
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1331280	1			T22	6938		T25	63		T28	40
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4907359	1			T22	15040		T23	465		T24	682
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3753155	1			T22	25045		T23	465		T24	654
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1342916	1			T22	7054		T25	93		T28	26
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1630546	1			T22	741		T25	98		T28	34
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	503924	1			T22	10385		T25	13		T30	15
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1336639	1			T22	7123		T25	47		T28	46
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4913892	1			T22	15040		T23	422		T24	573
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3754159	1			T22	25074		T23	508		T24	763
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1349378	1			T22	6927		T25	58		T28	28
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1625745	1			T22	753		T25	213		T28	42
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	500860	1			T22	10567		T25	40		T30	19
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1330505	1			T22	7027		T25	65		T28	21
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4900989	1			T22	15098		T23	395		T24	656
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3761030	1			T22	25215		T23	535		T24	680
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1349621	1			T22	7008		T25	68		T28	60
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1626526	1			T22	719		T25	169		T28	18
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	503187	1			T22	10148		T25	28		T30	25
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1333186	1			T22	7200		T25	55		T28	41
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4915253	1			T22	15256		T23	472		T24	626
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3747673	1			T22	25295		T23	458		T24	710
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1347368	1			T22	7067		T25	61		T28	42
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1628195	1			T22	710		T25	210		T28	50
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	503325	1			T22	10126		T25	25		T30	19
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1332725	1			T22	6934		T25	37		T28	26
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4914933	1			T22	14985		T23	512		T24	687
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3751066	1			T22	25381		T23	418		T24	649
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1345258	1			T22	6916		T25	75		T28	20
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1624703	1			T22	803		T25	163		T28	47
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	502156	1			T22	10005		T25	38		T30	27
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1336423	1			T22	7298		T25	32		T28	28
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4916429	1			T22	15046		T23	480		T24	646
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3740321	1			T22	25031		T23	450		T24	690
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1353071	1			T22	6964		T25	35		T28	32
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1622281	1			T22	780		T25	193		T28	23
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	504261	1			T22	10471		T25	32		T30	14
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1338176	1			T22	7096		T25	73		T28	28
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4899507	1			T22	15174		T23	535		T24	616
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3758502	1			T22	24930		T23	395		T24	720
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1345476	1			T22	6893		T25	48		T28	28
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1629344	1			T22	731		T25	231		T28	40
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	503380	1			T22	10606		T25	52		T30	16
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1338330	1			T22	7054		T25	51		T28	40
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4909891	1			T22	15101		T23	416		T24	652
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3751065	1			T22	25201		T23	514		T24	684
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1350731	1			T22	6897		T25	68		T28	50
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1625621	1			T22	728		T25	145		T28	21
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	503066	1			T22	10717		T25	31		T30	15
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1334165	1			T22	6744		T25	44		T28	46
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4920358	1			T22	15083		T23	478		T24	695
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3740122	1			T22	25504		T23	452		T24	641
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1349211	1			T22	6980		T25	68		T28	25
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1624461	1			T22	619		T25	183		T28	28
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	503105	1			T22	10132		T25	24		T30	23
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1337282	1			T22	7070		T25	38		T28	32
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4909242	1			T22	15003		T23	501		T24	599
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3749578	1			T22	25487		T23	429		T24	737
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1341024	1			T22	6839		T25	47		T28	30
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1633331	1			T22	735		T25	213		T28	50
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	505019	1			T22	10440		T25	44		T30	15
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1336345	1			T22	6884		T25	77		T28	26
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4914310	1			T22	15111		T23	423		T24	666
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3741785	1			T22	25306		T23	507		T24	670
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1345872	1			T22	7066		T25	33		T28	28
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1632621	1			T22	685		T25	246		T28	47
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	506225	1			T22	10358		T25	37		T30	16
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1333726	1			T22	6862		T25	51		T28	16
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4914248	1			T22	15188		T23	509		T24	607
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3746796	1			T22	25227		T23	421		T24	729
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1343203	1			T22	6992		T25	57		T28	18
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1630142	1			T22	696		T25	172		T28	50
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	504218	1			T22	10438		T25	31		T30	11
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1335932	1			T22	6847		T25	67		T28	26
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4917105	1			T22	15377		T23	499		T24	632
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3745110	1			T22	25836		T23	431		T24	704
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1345047	1			T22	7280		T25	40		T28	22
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1630079	1			T22	623		T25	206		T28	34
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	503865	1			T22	9559		T25	29		T30	31
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1333333	1			T22	6713		T25	91		T28	46
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4906823	1			T22	15051		T23	500		T24	575
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3755059	1			T22	25271		T23	430		T24	761
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1347613	1			T22	7136		T25	70		T28	38
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1627518	1			T22	760		T25	213		T28	37
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	501853	1			T22	10251		T25	41		T30	21
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1335673	1			T22	6919		T25	64		T28	30
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4905409	1			T22	15170		T23	534		T24	554
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3754213	1			T22	25221		T23	396		T24	782
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1346213	1			T22	7053		T25	47		T28	25
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1631059	1			T22	754		T25	185		T28	48
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	504862	1			T22	10151		T25	28		T30	9
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1332783	1			T22	7039		T25	72		T28	32

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal