Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[1]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[2]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[3]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[4]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[5]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[6]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[7]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[8]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[9]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[10]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[11]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[12]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[13]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[14]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[15]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[16]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[17]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[18]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[19]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[20]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[21]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[22]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[23]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[24]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[25]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[26]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[27]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[28]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[29]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[30]	13474539	1			T22	65388		T23	930		T24	1336
bins_for_gpio_bits[31]	13474539	1			T22	65388		T23	930		T24	1336

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

252253253

1

T22

730609

T23

14916

T24

20976

auto[1]

178931995

1

T22

136180

T23

14844

T24

21776

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

252247342

1

T22

730801

T23

14916

T24

20976

auto[1]

178937906

1

T22

136161

T23

14844

T24

21776

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7632000	1			T22	21714		T23	497		T24	665
bins_for_gpio_bits[0]	auto[0]	auto[1]	240561	1			T22	1368		T25	11		T28	7
bins_for_gpio_bits[0]	auto[1]	auto[0]	240752	1			T22	1363		T25	11		T28	7
bins_for_gpio_bits[0]	auto[1]	auto[1]	5361226	1			T22	40943		T23	433		T24	671
bins_for_gpio_bits[1]	auto[0]	auto[0]	7638744	1			T22	21303		T23	421		T24	786
bins_for_gpio_bits[1]	auto[0]	auto[1]	240750	1			T22	1330		T25	7		T28	9
bins_for_gpio_bits[1]	auto[1]	auto[0]	240946	1			T22	1321		T25	7		T28	9
bins_for_gpio_bits[1]	auto[1]	auto[1]	5354099	1			T22	41434		T23	509		T24	550
bins_for_gpio_bits[2]	auto[0]	auto[0]	7640376	1			T22	21744		T23	481		T24	672
bins_for_gpio_bits[2]	auto[0]	auto[1]	239875	1			T22	1342		T25	12		T28	11
bins_for_gpio_bits[2]	auto[1]	auto[0]	240107	1			T22	1334		T25	12		T28	11
bins_for_gpio_bits[2]	auto[1]	auto[1]	5354181	1			T22	40968		T23	449		T24	664
bins_for_gpio_bits[3]	auto[0]	auto[0]	7640202	1			T22	21453		T23	476		T24	753
bins_for_gpio_bits[3]	auto[0]	auto[1]	239472	1			T22	1285		T25	15		T28	8
bins_for_gpio_bits[3]	auto[1]	auto[0]	239628	1			T22	1281		T25	15		T28	8
bins_for_gpio_bits[3]	auto[1]	auto[1]	5355237	1			T22	41369		T23	454		T24	583
bins_for_gpio_bits[4]	auto[0]	auto[0]	7627244	1			T22	21535		T23	371		T24	649
bins_for_gpio_bits[4]	auto[0]	auto[1]	240914	1			T22	1314		T25	10		T28	9
bins_for_gpio_bits[4]	auto[1]	auto[0]	241090	1			T22	1307		T25	10		T28	9
bins_for_gpio_bits[4]	auto[1]	auto[1]	5365291	1			T22	41232		T23	559		T24	687
bins_for_gpio_bits[5]	auto[0]	auto[0]	7644955	1			T22	21278		T23	429		T24	722
bins_for_gpio_bits[5]	auto[0]	auto[1]	239815	1			T22	1273		T25	8		T28	13
bins_for_gpio_bits[5]	auto[1]	auto[0]	240004	1			T22	1269		T25	8		T28	14
bins_for_gpio_bits[5]	auto[1]	auto[1]	5349765	1			T22	41568		T23	501		T24	614
bins_for_gpio_bits[6]	auto[0]	auto[0]	7649474	1			T22	21104		T23	416		T24	650
bins_for_gpio_bits[6]	auto[0]	auto[1]	239641	1			T22	1257		T25	12		T28	7
bins_for_gpio_bits[6]	auto[1]	auto[0]	239824	1			T22	1252		T25	12		T28	7
bins_for_gpio_bits[6]	auto[1]	auto[1]	5345600	1			T22	41775		T23	514		T24	686
bins_for_gpio_bits[7]	auto[0]	auto[0]	7650435	1			T22	21729		T23	433		T24	642
bins_for_gpio_bits[7]	auto[0]	auto[1]	239617	1			T22	1330		T25	12		T28	12
bins_for_gpio_bits[7]	auto[1]	auto[0]	239789	1			T22	1323		T25	12		T28	12
bins_for_gpio_bits[7]	auto[1]	auto[1]	5344698	1			T22	41006		T23	497		T24	694
bins_for_gpio_bits[8]	auto[0]	auto[0]	7640726	1			T22	21592		T23	484		T24	624
bins_for_gpio_bits[8]	auto[0]	auto[1]	239735	1			T22	1356		T25	11		T28	8
bins_for_gpio_bits[8]	auto[1]	auto[0]	239902	1			T22	1348		T25	11		T28	8
bins_for_gpio_bits[8]	auto[1]	auto[1]	5354176	1			T22	41092		T23	446		T24	712
bins_for_gpio_bits[9]	auto[0]	auto[0]	7637460	1			T22	21743		T23	458		T24	640
bins_for_gpio_bits[9]	auto[0]	auto[1]	240722	1			T22	1344		T25	12		T28	12
bins_for_gpio_bits[9]	auto[1]	auto[0]	240938	1			T22	1339		T25	12		T28	12
bins_for_gpio_bits[9]	auto[1]	auto[1]	5355419	1			T22	40962		T23	472		T24	696
bins_for_gpio_bits[10]	auto[0]	auto[0]	7631269	1			T22	21600		T23	460		T24	752
bins_for_gpio_bits[10]	auto[0]	auto[1]	239747	1			T22	1298		T25	15		T28	6
bins_for_gpio_bits[10]	auto[1]	auto[0]	239945	1			T22	1292		T25	15		T28	6
bins_for_gpio_bits[10]	auto[1]	auto[1]	5363578	1			T22	41198		T23	470		T24	584
bins_for_gpio_bits[11]	auto[0]	auto[0]	7651892	1			T22	21261		T23	418		T24	661
bins_for_gpio_bits[11]	auto[0]	auto[1]	239529	1			T22	1304		T25	15		T28	8
bins_for_gpio_bits[11]	auto[1]	auto[0]	239741	1			T22	1294		T25	15		T28	9
bins_for_gpio_bits[11]	auto[1]	auto[1]	5343377	1			T22	41529		T23	512		T24	675
bins_for_gpio_bits[12]	auto[0]	auto[0]	7639365	1			T22	21692		T23	534		T24	621
bins_for_gpio_bits[12]	auto[0]	auto[1]	239558	1			T22	1335		T25	14		T28	11
bins_for_gpio_bits[12]	auto[1]	auto[0]	239755	1			T22	1332		T25	14		T28	11
bins_for_gpio_bits[12]	auto[1]	auto[1]	5355861	1			T22	41029		T23	396		T24	715
bins_for_gpio_bits[13]	auto[0]	auto[0]	7639117	1			T22	21513		T23	550		T24	671
bins_for_gpio_bits[13]	auto[0]	auto[1]	239863	1			T22	1311		T25	14		T28	6
bins_for_gpio_bits[13]	auto[1]	auto[0]	240079	1			T22	1308		T25	14		T28	6
bins_for_gpio_bits[13]	auto[1]	auto[1]	5355480	1			T22	41256		T23	380		T24	665
bins_for_gpio_bits[14]	auto[0]	auto[0]	7634985	1			T22	21013		T23	510		T24	678
bins_for_gpio_bits[14]	auto[0]	auto[1]	240207	1			T22	1313		T25	12		T28	8
bins_for_gpio_bits[14]	auto[1]	auto[0]	240400	1			T22	1306		T25	12		T28	9
bins_for_gpio_bits[14]	auto[1]	auto[1]	5358947	1			T22	41756		T23	420		T24	658
bins_for_gpio_bits[15]	auto[0]	auto[0]	7639661	1			T22	21816		T23	461		T24	584
bins_for_gpio_bits[15]	auto[0]	auto[1]	239881	1			T22	1319		T25	15		T28	6
bins_for_gpio_bits[15]	auto[1]	auto[0]	240043	1			T22	1314		T25	15		T28	6
bins_for_gpio_bits[15]	auto[1]	auto[1]	5354954	1			T22	40939		T23	469		T24	752
bins_for_gpio_bits[16]	auto[0]	auto[0]	7642604	1			T22	21533		T23	376		T24	740
bins_for_gpio_bits[16]	auto[0]	auto[1]	239680	1			T22	1381		T25	12		T28	12
bins_for_gpio_bits[16]	auto[1]	auto[0]	239879	1			T22	1371		T25	12		T28	12
bins_for_gpio_bits[16]	auto[1]	auto[1]	5352376	1			T22	41103		T23	554		T24	596
bins_for_gpio_bits[17]	auto[0]	auto[0]	7640408	1			T22	21489		T23	465		T24	682
bins_for_gpio_bits[17]	auto[0]	auto[1]	240236	1			T22	1352		T25	6		T28	11
bins_for_gpio_bits[17]	auto[1]	auto[0]	240413	1			T22	1346		T25	6		T28	11
bins_for_gpio_bits[17]	auto[1]	auto[1]	5353482	1			T22	41201		T23	465		T24	654
bins_for_gpio_bits[18]	auto[0]	auto[0]	7649132	1			T22	21404		T23	422		T24	573
bins_for_gpio_bits[18]	auto[0]	auto[1]	239677	1			T22	1323		T25	13		T28	8
bins_for_gpio_bits[18]	auto[1]	auto[0]	239883	1			T22	1316		T25	13		T28	9
bins_for_gpio_bits[18]	auto[1]	auto[1]	5345847	1			T22	41345		T23	508		T24	763
bins_for_gpio_bits[19]	auto[0]	auto[0]	7637080	1			T22	21513		T23	395		T24	656
bins_for_gpio_bits[19]	auto[0]	auto[1]	239858	1			T22	1318		T25	14		T28	8
bins_for_gpio_bits[19]	auto[1]	auto[0]	240056	1			T22	1312		T25	14		T28	9
bins_for_gpio_bits[19]	auto[1]	auto[1]	5357545	1			T22	41245		T23	535		T24	680
bins_for_gpio_bits[20]	auto[0]	auto[0]	7650931	1			T22	21676		T23	472		T24	626
bins_for_gpio_bits[20]	auto[0]	auto[1]	239677	1			T22	1363		T25	7		T28	7
bins_for_gpio_bits[20]	auto[1]	auto[0]	239885	1			T22	1357		T25	7		T28	7
bins_for_gpio_bits[20]	auto[1]	auto[1]	5344046	1			T22	40992		T23	458		T24	710
bins_for_gpio_bits[21]	auto[0]	auto[0]	7644819	1			T22	21368		T23	512		T24	687
bins_for_gpio_bits[21]	auto[0]	auto[1]	239876	1			T22	1344		T25	9		T28	8
bins_for_gpio_bits[21]	auto[1]	auto[0]	240075	1			T22	1336		T25	9		T28	8
bins_for_gpio_bits[21]	auto[1]	auto[1]	5349769	1			T22	41340		T23	418		T24	649
bins_for_gpio_bits[22]	auto[0]	auto[0]	7651738	1			T22	21473		T23	480		T24	646
bins_for_gpio_bits[22]	auto[0]	auto[1]	239860	1			T22	1325		T25	13		T28	7
bins_for_gpio_bits[22]	auto[1]	auto[0]	240043	1			T22	1317		T25	13		T28	7
bins_for_gpio_bits[22]	auto[1]	auto[1]	5342898	1			T22	41273		T23	450		T24	690
bins_for_gpio_bits[23]	auto[0]	auto[0]	7633809	1			T22	21498		T23	535		T24	616
bins_for_gpio_bits[23]	auto[0]	auto[1]	240388	1			T22	1306		T25	9		T28	9
bins_for_gpio_bits[23]	auto[1]	auto[0]	240518	1			T22	1300		T25	9		T28	9
bins_for_gpio_bits[23]	auto[1]	auto[1]	5359824	1			T22	41284		T23	395		T24	720
bins_for_gpio_bits[24]	auto[0]	auto[0]	7646235	1			T22	21376		T23	416		T24	652
bins_for_gpio_bits[24]	auto[0]	auto[1]	239840	1			T22	1355		T25	12		T28	10
bins_for_gpio_bits[24]	auto[1]	auto[0]	240008	1			T22	1350		T25	12		T28	10
bins_for_gpio_bits[24]	auto[1]	auto[1]	5348456	1			T22	41307		T23	514		T24	684
bins_for_gpio_bits[25]	auto[0]	auto[0]	7654118	1			T22	21355		T23	478		T24	695
bins_for_gpio_bits[25]	auto[0]	auto[1]	239742	1			T22	1332		T25	9		T28	7
bins_for_gpio_bits[25]	auto[1]	auto[0]	239912	1			T22	1327		T25	9		T28	7
bins_for_gpio_bits[25]	auto[1]	auto[1]	5340767	1			T22	41374		T23	452		T24	641
bins_for_gpio_bits[26]	auto[0]	auto[0]	7643399	1			T22	21289		T23	501		T24	599
bins_for_gpio_bits[26]	auto[0]	auto[1]	240009	1			T22	1291		T25	16		T28	7
bins_for_gpio_bits[26]	auto[1]	auto[0]	240198	1			T22	1288		T25	16		T28	7
bins_for_gpio_bits[26]	auto[1]	auto[1]	5350933	1			T22	41520		T23	429		T24	737
bins_for_gpio_bits[27]	auto[0]	auto[0]	7652820	1			T22	21532		T23	423		T24	666
bins_for_gpio_bits[27]	auto[0]	auto[1]	239836	1			T22	1336		T25	9		T28	6
bins_for_gpio_bits[27]	auto[1]	auto[0]	239983	1			T22	1330		T25	9		T28	6
bins_for_gpio_bits[27]	auto[1]	auto[1]	5341900	1			T22	41190		T23	507		T24	670
bins_for_gpio_bits[28]	auto[0]	auto[0]	7647197	1			T22	21555		T23	509		T24	607
bins_for_gpio_bits[28]	auto[0]	auto[1]	240257	1			T22	1323		T25	14		T28	7
bins_for_gpio_bits[28]	auto[1]	auto[0]	240396	1			T22	1321		T25	14		T28	7
bins_for_gpio_bits[28]	auto[1]	auto[1]	5346689	1			T22	41189		T23	421		T24	729
bins_for_gpio_bits[29]	auto[0]	auto[0]	7652473	1			T22	21885		T23	499		T24	632
bins_for_gpio_bits[29]	auto[0]	auto[1]	239570	1			T22	1400		T25	16		T28	10
bins_for_gpio_bits[29]	auto[1]	auto[0]	239758	1			T22	1395		T25	16		T28	10
bins_for_gpio_bits[29]	auto[1]	auto[1]	5342738	1			T22	40708		T23	431		T24	704
bins_for_gpio_bits[30]	auto[0]	auto[0]	7641601	1			T22	21611		T23	500		T24	575
bins_for_gpio_bits[30]	auto[0]	auto[1]	240144	1			T22	1343		T25	11		T28	8
bins_for_gpio_bits[30]	auto[1]	auto[0]	240353	1			T22	1336		T25	11		T28	8
bins_for_gpio_bits[30]	auto[1]	auto[1]	5352441	1			T22	41098		T23	430		T24	761
bins_for_gpio_bits[31]	auto[0]	auto[0]	7642309	1			T22	21608		T23	534		T24	554
bins_for_gpio_bits[31]	auto[0]	auto[1]	240227	1			T22	1375		T25	14		T28	9
bins_for_gpio_bits[31]	auto[1]	auto[0]	240372	1			T22	1369		T25	14		T28	9
bins_for_gpio_bits[31]	auto[1]	auto[1]	5351631	1			T22	41036		T23	396		T24	782