Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7849055 |
1 |
|
|
T22 |
37258 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5857384 |
1 |
|
|
T22 |
29012 |
|
T27 |
105 |
|
T2 |
11972 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12970243 |
1 |
|
|
T22 |
62405 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
736196 |
1 |
|
|
T22 |
3865 |
|
T27 |
54 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7932377 |
1 |
|
|
T22 |
37660 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5774062 |
1 |
|
|
T22 |
28610 |
|
T27 |
305 |
|
T1 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2520204 |
1 |
|
|
T22 |
12467 |
|
T27 |
203 |
|
T1 |
7 |
| auto[1] |
auto[0] |
auto[1] |
367741 |
1 |
|
|
T22 |
1928 |
|
T27 |
45 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2517662 |
1 |
|
|
T22 |
12278 |
|
T27 |
48 |
|
T2 |
4874 |
| auto[1] |
auto[1] |
auto[1] |
368455 |
1 |
|
|
T22 |
1937 |
|
T27 |
9 |
|
T2 |
975 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7877255 |
1 |
|
|
T22 |
38263 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5829184 |
1 |
|
|
T22 |
28007 |
|
T27 |
187 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12961552 |
1 |
|
|
T22 |
62240 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
744887 |
1 |
|
|
T22 |
4030 |
|
T27 |
38 |
|
T2 |
1878 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7874093 |
1 |
|
|
T22 |
36736 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5832346 |
1 |
|
|
T22 |
29534 |
|
T27 |
197 |
|
T1 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2549940 |
1 |
|
|
T22 |
13839 |
|
T27 |
64 |
|
T2 |
4787 |
| auto[1] |
auto[0] |
auto[1] |
373139 |
1 |
|
|
T22 |
2187 |
|
T27 |
15 |
|
T2 |
897 |
| auto[1] |
auto[1] |
auto[0] |
2537519 |
1 |
|
|
T22 |
11665 |
|
T27 |
95 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[1] |
371748 |
1 |
|
|
T22 |
1843 |
|
T27 |
23 |
|
T2 |
981 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7910445 |
1 |
|
|
T22 |
37951 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5795994 |
1 |
|
|
T22 |
28319 |
|
T27 |
280 |
|
T1 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12960771 |
1 |
|
|
T22 |
62183 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
745668 |
1 |
|
|
T22 |
4087 |
|
T27 |
52 |
|
T2 |
1937 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7866097 |
1 |
|
|
T22 |
36045 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5840342 |
1 |
|
|
T22 |
30225 |
|
T27 |
263 |
|
T1 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2564960 |
1 |
|
|
T22 |
13980 |
|
T27 |
128 |
|
T2 |
5477 |
| auto[1] |
auto[0] |
auto[1] |
375713 |
1 |
|
|
T22 |
2168 |
|
T27 |
34 |
|
T2 |
1066 |
| auto[1] |
auto[1] |
auto[0] |
2529714 |
1 |
|
|
T22 |
12158 |
|
T27 |
83 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[1] |
369955 |
1 |
|
|
T22 |
1919 |
|
T27 |
18 |
|
T2 |
871 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7904095 |
1 |
|
|
T22 |
37573 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5802344 |
1 |
|
|
T22 |
28697 |
|
T27 |
170 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12964991 |
1 |
|
|
T22 |
62279 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
741448 |
1 |
|
|
T22 |
3991 |
|
T27 |
46 |
|
T2 |
1654 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7906301 |
1 |
|
|
T22 |
36315 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5800138 |
1 |
|
|
T22 |
29955 |
|
T27 |
225 |
|
T1 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2548462 |
1 |
|
|
T22 |
13170 |
|
T27 |
140 |
|
T2 |
3994 |
| auto[1] |
auto[0] |
auto[1] |
373744 |
1 |
|
|
T22 |
2042 |
|
T27 |
35 |
|
T2 |
760 |
| auto[1] |
auto[1] |
auto[0] |
2510228 |
1 |
|
|
T22 |
12794 |
|
T27 |
39 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[1] |
367704 |
1 |
|
|
T22 |
1949 |
|
T27 |
11 |
|
T2 |
894 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7871527 |
1 |
|
|
T22 |
35615 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5834912 |
1 |
|
|
T22 |
30655 |
|
T27 |
150 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12965438 |
1 |
|
|
T22 |
62217 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
741001 |
1 |
|
|
T22 |
4053 |
|
T27 |
59 |
|
T2 |
1806 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7898366 |
1 |
|
|
T22 |
36133 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5808073 |
1 |
|
|
T22 |
30137 |
|
T27 |
352 |
|
T1 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2531145 |
1 |
|
|
T22 |
12614 |
|
T27 |
208 |
|
T1 |
7 |
| auto[1] |
auto[0] |
auto[1] |
369589 |
1 |
|
|
T22 |
1928 |
|
T27 |
40 |
|
T2 |
877 |
| auto[1] |
auto[1] |
auto[0] |
2535927 |
1 |
|
|
T22 |
13470 |
|
T27 |
85 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[1] |
371412 |
1 |
|
|
T22 |
2125 |
|
T27 |
19 |
|
T2 |
929 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7912738 |
1 |
|
|
T22 |
37660 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5793701 |
1 |
|
|
T22 |
28610 |
|
T27 |
144 |
|
T2 |
11448 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12960714 |
1 |
|
|
T22 |
62598 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
745725 |
1 |
|
|
T22 |
3672 |
|
T27 |
80 |
|
T2 |
1661 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7872158 |
1 |
|
|
T22 |
38430 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5834281 |
1 |
|
|
T22 |
27840 |
|
T27 |
384 |
|
T1 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2572540 |
1 |
|
|
T22 |
12088 |
|
T27 |
192 |
|
T1 |
9 |
| auto[1] |
auto[0] |
auto[1] |
378237 |
1 |
|
|
T22 |
1799 |
|
T27 |
50 |
|
T2 |
760 |
| auto[1] |
auto[1] |
auto[0] |
2516016 |
1 |
|
|
T22 |
12080 |
|
T27 |
112 |
|
T2 |
4950 |
| auto[1] |
auto[1] |
auto[1] |
367488 |
1 |
|
|
T22 |
1873 |
|
T27 |
30 |
|
T2 |
901 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7876645 |
1 |
|
|
T22 |
37043 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5829794 |
1 |
|
|
T22 |
29227 |
|
T27 |
195 |
|
T1 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12965135 |
1 |
|
|
T22 |
62086 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
741304 |
1 |
|
|
T22 |
4184 |
|
T27 |
31 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7901123 |
1 |
|
|
T22 |
35893 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5805316 |
1 |
|
|
T22 |
30377 |
|
T27 |
156 |
|
T1 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2540334 |
1 |
|
|
T22 |
13058 |
|
T27 |
71 |
|
T1 |
15 |
| auto[1] |
auto[0] |
auto[1] |
371264 |
1 |
|
|
T22 |
2004 |
|
T27 |
18 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2523678 |
1 |
|
|
T22 |
13135 |
|
T27 |
54 |
|
T2 |
4842 |
| auto[1] |
auto[1] |
auto[1] |
370040 |
1 |
|
|
T22 |
2180 |
|
T27 |
13 |
|
T2 |
878 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7846471 |
1 |
|
|
T22 |
36477 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5859968 |
1 |
|
|
T22 |
29793 |
|
T27 |
257 |
|
T1 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12960261 |
1 |
|
|
T22 |
62389 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
746178 |
1 |
|
|
T22 |
3881 |
|
T27 |
9 |
|
T2 |
1881 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7870362 |
1 |
|
|
T22 |
36892 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5836077 |
1 |
|
|
T22 |
29378 |
|
T27 |
51 |
|
T1 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2528560 |
1 |
|
|
T22 |
12853 |
|
T1 |
12 |
|
T2 |
4503 |
| auto[1] |
auto[0] |
auto[1] |
369770 |
1 |
|
|
T22 |
1994 |
|
T2 |
888 |
|
T14 |
1277 |
| auto[1] |
auto[1] |
auto[0] |
2561339 |
1 |
|
|
T22 |
12644 |
|
T27 |
42 |
|
T2 |
5179 |
| auto[1] |
auto[1] |
auto[1] |
376408 |
1 |
|
|
T22 |
1887 |
|
T27 |
9 |
|
T2 |
993 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7903293 |
1 |
|
|
T22 |
37109 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5803146 |
1 |
|
|
T22 |
29161 |
|
T27 |
221 |
|
T1 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12964832 |
1 |
|
|
T22 |
62393 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
741607 |
1 |
|
|
T22 |
3877 |
|
T27 |
39 |
|
T2 |
1607 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7891295 |
1 |
|
|
T22 |
37271 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5815144 |
1 |
|
|
T22 |
28999 |
|
T27 |
177 |
|
T1 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2534032 |
1 |
|
|
T22 |
12697 |
|
T27 |
52 |
|
T1 |
5 |
| auto[1] |
auto[0] |
auto[1] |
370109 |
1 |
|
|
T22 |
1960 |
|
T27 |
16 |
|
T2 |
823 |
| auto[1] |
auto[1] |
auto[0] |
2539505 |
1 |
|
|
T22 |
12425 |
|
T27 |
86 |
|
T2 |
4536 |
| auto[1] |
auto[1] |
auto[1] |
371498 |
1 |
|
|
T22 |
1917 |
|
T27 |
23 |
|
T2 |
784 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7873816 |
1 |
|
|
T22 |
36929 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5832623 |
1 |
|
|
T22 |
29341 |
|
T27 |
299 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12963343 |
1 |
|
|
T22 |
62726 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
743096 |
1 |
|
|
T22 |
3544 |
|
T27 |
52 |
|
T2 |
1903 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7889757 |
1 |
|
|
T22 |
39038 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5816682 |
1 |
|
|
T22 |
27232 |
|
T27 |
279 |
|
T1 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2538014 |
1 |
|
|
T22 |
11693 |
|
T27 |
68 |
|
T1 |
5 |
| auto[1] |
auto[0] |
auto[1] |
372504 |
1 |
|
|
T22 |
1672 |
|
T27 |
18 |
|
T2 |
1142 |
| auto[1] |
auto[1] |
auto[0] |
2535572 |
1 |
|
|
T22 |
11995 |
|
T27 |
159 |
|
T2 |
4181 |
| auto[1] |
auto[1] |
auto[1] |
370592 |
1 |
|
|
T22 |
1872 |
|
T27 |
34 |
|
T2 |
761 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7853893 |
1 |
|
|
T22 |
37748 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5852546 |
1 |
|
|
T22 |
28522 |
|
T27 |
216 |
|
T2 |
12471 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12965618 |
1 |
|
|
T22 |
62079 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
740821 |
1 |
|
|
T22 |
4191 |
|
T27 |
57 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7902684 |
1 |
|
|
T22 |
35808 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5803755 |
1 |
|
|
T22 |
30462 |
|
T27 |
300 |
|
T1 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2530428 |
1 |
|
|
T22 |
13558 |
|
T27 |
158 |
|
T1 |
11 |
| auto[1] |
auto[0] |
auto[1] |
370813 |
1 |
|
|
T22 |
2227 |
|
T27 |
36 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2532506 |
1 |
|
|
T22 |
12713 |
|
T27 |
85 |
|
T2 |
5082 |
| auto[1] |
auto[1] |
auto[1] |
370008 |
1 |
|
|
T22 |
1964 |
|
T27 |
21 |
|
T2 |
928 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7867315 |
1 |
|
|
T22 |
38247 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5839124 |
1 |
|
|
T22 |
28023 |
|
T27 |
200 |
|
T1 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12962934 |
1 |
|
|
T22 |
62066 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
743505 |
1 |
|
|
T22 |
4204 |
|
T27 |
71 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7888665 |
1 |
|
|
T22 |
35685 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5817774 |
1 |
|
|
T22 |
30585 |
|
T27 |
347 |
|
T1 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2537123 |
1 |
|
|
T22 |
13508 |
|
T27 |
188 |
|
T1 |
14 |
| auto[1] |
auto[0] |
auto[1] |
370973 |
1 |
|
|
T22 |
2228 |
|
T27 |
45 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2537146 |
1 |
|
|
T22 |
12873 |
|
T27 |
88 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[1] |
372532 |
1 |
|
|
T22 |
1976 |
|
T27 |
26 |
|
T2 |
1089 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7848827 |
1 |
|
|
T22 |
36744 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5857612 |
1 |
|
|
T22 |
29526 |
|
T27 |
45 |
|
T1 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12963502 |
1 |
|
|
T22 |
62387 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
742937 |
1 |
|
|
T22 |
3883 |
|
T27 |
25 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7887886 |
1 |
|
|
T22 |
37992 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5818553 |
1 |
|
|
T22 |
28278 |
|
T27 |
127 |
|
T1 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2515334 |
1 |
|
|
T22 |
12275 |
|
T27 |
100 |
|
T1 |
9 |
| auto[1] |
auto[0] |
auto[1] |
367520 |
1 |
|
|
T22 |
1924 |
|
T27 |
25 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2560282 |
1 |
|
|
T22 |
12120 |
|
T27 |
2 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[1] |
375417 |
1 |
|
|
T22 |
1959 |
|
T2 |
864 |
|
T14 |
1741 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7889847 |
1 |
|
|
T22 |
38570 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5816592 |
1 |
|
|
T22 |
27700 |
|
T27 |
217 |
|
T2 |
10613 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12962778 |
1 |
|
|
T22 |
61760 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
743661 |
1 |
|
|
T22 |
4510 |
|
T27 |
69 |
|
T2 |
1659 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7882310 |
1 |
|
|
T22 |
34121 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5824129 |
1 |
|
|
T22 |
32149 |
|
T27 |
349 |
|
T1 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2555094 |
1 |
|
|
T22 |
15618 |
|
T27 |
146 |
|
T1 |
8 |
| auto[1] |
auto[0] |
auto[1] |
374699 |
1 |
|
|
T22 |
2594 |
|
T27 |
34 |
|
T2 |
880 |
| auto[1] |
auto[1] |
auto[0] |
2525374 |
1 |
|
|
T22 |
12021 |
|
T27 |
134 |
|
T2 |
4258 |
| auto[1] |
auto[1] |
auto[1] |
368962 |
1 |
|
|
T22 |
1916 |
|
T27 |
35 |
|
T2 |
779 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7889307 |
1 |
|
|
T22 |
39235 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5817132 |
1 |
|
|
T22 |
27035 |
|
T27 |
207 |
|
T2 |
10867 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12961141 |
1 |
|
|
T22 |
62197 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
745298 |
1 |
|
|
T22 |
4073 |
|
T27 |
52 |
|
T2 |
1636 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7869245 |
1 |
|
|
T22 |
36416 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5837194 |
1 |
|
|
T22 |
29854 |
|
T27 |
238 |
|
T1 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2550441 |
1 |
|
|
T22 |
13083 |
|
T27 |
144 |
|
T1 |
7 |
| auto[1] |
auto[0] |
auto[1] |
373696 |
1 |
|
|
T22 |
2083 |
|
T27 |
42 |
|
T2 |
894 |
| auto[1] |
auto[1] |
auto[0] |
2541455 |
1 |
|
|
T22 |
12698 |
|
T27 |
42 |
|
T2 |
4166 |
| auto[1] |
auto[1] |
auto[1] |
371602 |
1 |
|
|
T22 |
1990 |
|
T27 |
10 |
|
T2 |
742 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7872995 |
1 |
|
|
T22 |
35984 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5833444 |
1 |
|
|
T22 |
30286 |
|
T27 |
344 |
|
T1 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12959680 |
1 |
|
|
T22 |
62153 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
746759 |
1 |
|
|
T22 |
4117 |
|
T27 |
41 |
|
T2 |
1697 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7860176 |
1 |
|
|
T22 |
36290 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5846263 |
1 |
|
|
T22 |
29980 |
|
T27 |
232 |
|
T1 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2560072 |
1 |
|
|
T22 |
11996 |
|
T27 |
85 |
|
T1 |
1 |
| auto[1] |
auto[0] |
auto[1] |
375470 |
1 |
|
|
T22 |
1842 |
|
T27 |
18 |
|
T2 |
812 |
| auto[1] |
auto[1] |
auto[0] |
2539432 |
1 |
|
|
T22 |
13867 |
|
T27 |
106 |
|
T2 |
4375 |
| auto[1] |
auto[1] |
auto[1] |
371289 |
1 |
|
|
T22 |
2275 |
|
T27 |
23 |
|
T2 |
885 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7863614 |
1 |
|
|
T22 |
37282 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5842825 |
1 |
|
|
T22 |
28988 |
|
T27 |
262 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12958433 |
1 |
|
|
T22 |
62493 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
748006 |
1 |
|
|
T22 |
3777 |
|
T27 |
30 |
|
T2 |
1735 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7856176 |
1 |
|
|
T22 |
38364 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5850263 |
1 |
|
|
T22 |
27906 |
|
T27 |
125 |
|
T1 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2550423 |
1 |
|
|
T22 |
11797 |
|
T27 |
26 |
|
T1 |
10 |
| auto[1] |
auto[0] |
auto[1] |
373799 |
1 |
|
|
T22 |
1850 |
|
T27 |
10 |
|
T2 |
754 |
| auto[1] |
auto[1] |
auto[0] |
2551834 |
1 |
|
|
T22 |
12332 |
|
T27 |
69 |
|
T2 |
5484 |
| auto[1] |
auto[1] |
auto[1] |
374207 |
1 |
|
|
T22 |
1927 |
|
T27 |
20 |
|
T2 |
981 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7875724 |
1 |
|
|
T22 |
37179 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5830715 |
1 |
|
|
T22 |
29091 |
|
T27 |
231 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12968377 |
1 |
|
|
T22 |
62397 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
738062 |
1 |
|
|
T22 |
3873 |
|
T27 |
39 |
|
T2 |
1781 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7901799 |
1 |
|
|
T22 |
37186 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5804640 |
1 |
|
|
T22 |
29084 |
|
T27 |
232 |
|
T1 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2534059 |
1 |
|
|
T22 |
12770 |
|
T27 |
87 |
|
T1 |
4 |
| auto[1] |
auto[0] |
auto[1] |
368473 |
1 |
|
|
T22 |
1917 |
|
T27 |
21 |
|
T2 |
907 |
| auto[1] |
auto[1] |
auto[0] |
2532519 |
1 |
|
|
T22 |
12441 |
|
T27 |
106 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[1] |
369589 |
1 |
|
|
T22 |
1956 |
|
T27 |
18 |
|
T2 |
874 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7893223 |
1 |
|
|
T22 |
37331 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5813216 |
1 |
|
|
T22 |
28939 |
|
T27 |
204 |
|
T1 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12961720 |
1 |
|
|
T22 |
62075 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
744719 |
1 |
|
|
T22 |
4195 |
|
T27 |
29 |
|
T2 |
1781 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7878134 |
1 |
|
|
T22 |
35014 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5828305 |
1 |
|
|
T22 |
31256 |
|
T27 |
125 |
|
T1 |
14 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2552833 |
1 |
|
|
T22 |
13923 |
|
T27 |
43 |
|
T1 |
10 |
| auto[1] |
auto[0] |
auto[1] |
374643 |
1 |
|
|
T22 |
2190 |
|
T27 |
15 |
|
T2 |
765 |
| auto[1] |
auto[1] |
auto[0] |
2530753 |
1 |
|
|
T22 |
13138 |
|
T27 |
53 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[1] |
370076 |
1 |
|
|
T22 |
2005 |
|
T27 |
14 |
|
T2 |
1016 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7879120 |
1 |
|
|
T22 |
34497 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5827319 |
1 |
|
|
T22 |
31773 |
|
T27 |
223 |
|
T1 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12959902 |
1 |
|
|
T22 |
62108 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
746537 |
1 |
|
|
T22 |
4162 |
|
T27 |
30 |
|
T2 |
1763 |