Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7860196 |
1 |
|
|
T22 |
36826 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5846243 |
1 |
|
|
T22 |
29444 |
|
T27 |
283 |
|
T2 |
11340 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12967057 |
1 |
|
|
T22 |
62540 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
739382 |
1 |
|
|
T22 |
3730 |
|
T27 |
41 |
|
T2 |
1755 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7909239 |
1 |
|
|
T22 |
37445 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5797200 |
1 |
|
|
T22 |
28825 |
|
T27 |
211 |
|
T1 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2520453 |
1 |
|
|
T22 |
12643 |
|
T27 |
49 |
|
T1 |
20 |
| auto[1] |
auto[0] |
auto[1] |
368130 |
1 |
|
|
T22 |
1889 |
|
T27 |
10 |
|
T2 |
800 |
| auto[1] |
auto[1] |
auto[0] |
2537365 |
1 |
|
|
T22 |
12452 |
|
T27 |
121 |
|
T2 |
4927 |
| auto[1] |
auto[1] |
auto[1] |
371252 |
1 |
|
|
T22 |
1841 |
|
T27 |
31 |
|
T2 |
955 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |