Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7906044 |
1 |
|
|
T22 |
38136 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5800395 |
1 |
|
|
T22 |
28134 |
|
T27 |
286 |
|
T1 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12960032 |
1 |
|
|
T22 |
62358 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
746407 |
1 |
|
|
T22 |
3912 |
|
T27 |
17 |
|
T2 |
1787 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7864609 |
1 |
|
|
T22 |
36550 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5841830 |
1 |
|
|
T22 |
29720 |
|
T27 |
72 |
|
T1 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2558094 |
1 |
|
|
T22 |
12762 |
|
T27 |
37 |
|
T1 |
1 |
| auto[1] |
auto[0] |
auto[1] |
376340 |
1 |
|
|
T22 |
1920 |
|
T27 |
14 |
|
T2 |
840 |
| auto[1] |
auto[1] |
auto[0] |
2537329 |
1 |
|
|
T22 |
13046 |
|
T27 |
18 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[1] |
370067 |
1 |
|
|
T22 |
1992 |
|
T27 |
3 |
|
T2 |
947 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |