Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7879016 |
1 |
|
|
T22 |
38105 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5827423 |
1 |
|
|
T22 |
28165 |
|
T27 |
239 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12963152 |
1 |
|
|
T22 |
62243 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
743287 |
1 |
|
|
T22 |
4027 |
|
T27 |
61 |
|
T2 |
1961 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7890001 |
1 |
|
|
T22 |
36505 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5816438 |
1 |
|
|
T22 |
29765 |
|
T27 |
275 |
|
T1 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2534844 |
1 |
|
|
T22 |
13819 |
|
T27 |
95 |
|
T1 |
5 |
| auto[1] |
auto[0] |
auto[1] |
371099 |
1 |
|
|
T22 |
2258 |
|
T27 |
25 |
|
T2 |
867 |
| auto[1] |
auto[1] |
auto[0] |
2538307 |
1 |
|
|
T22 |
11919 |
|
T27 |
119 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[1] |
372188 |
1 |
|
|
T22 |
1769 |
|
T27 |
36 |
|
T2 |
1094 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |