Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7892766 |
1 |
|
|
T22 |
37089 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5813673 |
1 |
|
|
T22 |
29181 |
|
T27 |
151 |
|
T1 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12959283 |
1 |
|
|
T22 |
62389 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
747156 |
1 |
|
|
T22 |
3881 |
|
T27 |
89 |
|
T2 |
2045 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7864269 |
1 |
|
|
T22 |
36472 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5842170 |
1 |
|
|
T22 |
29798 |
|
T27 |
426 |
|
T1 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2555375 |
1 |
|
|
T22 |
12953 |
|
T27 |
262 |
|
T1 |
5 |
| auto[1] |
auto[0] |
auto[1] |
375530 |
1 |
|
|
T22 |
1948 |
|
T27 |
72 |
|
T2 |
1002 |
| auto[1] |
auto[1] |
auto[0] |
2539639 |
1 |
|
|
T22 |
12964 |
|
T27 |
75 |
|
T2 |
5482 |
| auto[1] |
auto[1] |
auto[1] |
371626 |
1 |
|
|
T22 |
1933 |
|
T27 |
17 |
|
T2 |
1043 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |