Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7904125 |
1 |
|
|
T22 |
35657 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5802314 |
1 |
|
|
T22 |
30613 |
|
T27 |
220 |
|
T2 |
12802 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12959892 |
1 |
|
|
T22 |
62347 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
746547 |
1 |
|
|
T22 |
3923 |
|
T27 |
50 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7864757 |
1 |
|
|
T22 |
37281 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5841682 |
1 |
|
|
T22 |
28989 |
|
T27 |
248 |
|
T1 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2548972 |
1 |
|
|
T22 |
12447 |
|
T27 |
108 |
|
T1 |
6 |
| auto[1] |
auto[0] |
auto[1] |
373623 |
1 |
|
|
T22 |
1930 |
|
T27 |
25 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2546163 |
1 |
|
|
T22 |
12619 |
|
T27 |
90 |
|
T2 |
5700 |
| auto[1] |
auto[1] |
auto[1] |
372924 |
1 |
|
|
T22 |
1993 |
|
T27 |
25 |
|
T2 |
1002 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |