Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7877255 |
1 |
|
|
T22 |
38263 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5829184 |
1 |
|
|
T22 |
28007 |
|
T27 |
187 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11252438 |
1 |
|
|
T22 |
49157 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
2454001 |
1 |
|
|
T22 |
17113 |
|
T27 |
157 |
|
T1 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7881068 |
1 |
|
|
T22 |
37833 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5825371 |
1 |
|
|
T22 |
28437 |
|
T27 |
300 |
|
T1 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1696773 |
1 |
|
|
T22 |
6055 |
|
T27 |
72 |
|
T1 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1232068 |
1 |
|
|
T22 |
9137 |
|
T27 |
86 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1674597 |
1 |
|
|
T22 |
5269 |
|
T27 |
71 |
|
T2 |
2997 |
| auto[1] |
auto[1] |
auto[1] |
1221933 |
1 |
|
|
T22 |
7976 |
|
T27 |
71 |
|
T2 |
2504 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |