Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7910445 |
1 |
|
|
T22 |
37951 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5795994 |
1 |
|
|
T22 |
28319 |
|
T27 |
280 |
|
T1 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11253824 |
1 |
|
|
T22 |
48990 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
2452615 |
1 |
|
|
T22 |
17280 |
|
T27 |
99 |
|
T2 |
5013 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7896675 |
1 |
|
|
T22 |
37519 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5809764 |
1 |
|
|
T22 |
28751 |
|
T27 |
216 |
|
T1 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1689875 |
1 |
|
|
T22 |
5945 |
|
T27 |
60 |
|
T1 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1235288 |
1 |
|
|
T22 |
9334 |
|
T27 |
43 |
|
T2 |
2777 |
| auto[1] |
auto[1] |
auto[0] |
1667274 |
1 |
|
|
T22 |
5526 |
|
T27 |
57 |
|
T2 |
2712 |
| auto[1] |
auto[1] |
auto[1] |
1217327 |
1 |
|
|
T22 |
7946 |
|
T27 |
56 |
|
T2 |
2236 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |