Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7904095 |
1 |
|
|
T22 |
37573 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5802344 |
1 |
|
|
T22 |
28697 |
|
T27 |
170 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11255496 |
1 |
|
|
T22 |
49162 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
2450943 |
1 |
|
|
T22 |
17108 |
|
T27 |
53 |
|
T1 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7883567 |
1 |
|
|
T22 |
38382 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5822872 |
1 |
|
|
T22 |
27888 |
|
T27 |
116 |
|
T1 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1688168 |
1 |
|
|
T22 |
5517 |
|
T27 |
43 |
|
T1 |
1 |
| auto[1] |
auto[0] |
auto[1] |
1228356 |
1 |
|
|
T22 |
8630 |
|
T27 |
31 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1683761 |
1 |
|
|
T22 |
5263 |
|
T27 |
20 |
|
T2 |
2626 |
| auto[1] |
auto[1] |
auto[1] |
1222587 |
1 |
|
|
T22 |
8478 |
|
T27 |
22 |
|
T1 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |