Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7871527 |
1 |
|
|
T22 |
35615 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5834912 |
1 |
|
|
T22 |
30655 |
|
T27 |
150 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11250303 |
1 |
|
|
T22 |
48966 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
2456136 |
1 |
|
|
T22 |
17304 |
|
T27 |
77 |
|
T1 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7887498 |
1 |
|
|
T22 |
37240 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5818941 |
1 |
|
|
T22 |
29030 |
|
T27 |
149 |
|
T1 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1693436 |
1 |
|
|
T22 |
5552 |
|
T27 |
37 |
|
T1 |
3 |
| auto[1] |
auto[0] |
auto[1] |
1231734 |
1 |
|
|
T22 |
8266 |
|
T27 |
28 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[0] |
1669369 |
1 |
|
|
T22 |
6174 |
|
T27 |
35 |
|
T2 |
3175 |
| auto[1] |
auto[1] |
auto[1] |
1224402 |
1 |
|
|
T22 |
9038 |
|
T27 |
49 |
|
T2 |
2529 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |