Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7863876 |
1 |
|
|
T22 |
35853 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5842563 |
1 |
|
|
T22 |
30417 |
|
T27 |
142 |
|
T1 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2557414 |
1 |
|
|
T22 |
12022 |
|
T27 |
32 |
|
T1 |
7 |
| auto[1] |
auto[0] |
auto[1] |
375985 |
1 |
|
|
T22 |
1906 |
|
T27 |
9 |
|
T2 |
1088 |
| auto[1] |
auto[1] |
auto[0] |
2538612 |
1 |
|
|
T22 |
14233 |
|
T27 |
80 |
|
T2 |
3777 |
| auto[1] |
auto[1] |
auto[1] |
370552 |
1 |
|
|
T22 |
2256 |
|
T27 |
21 |
|
T2 |
675 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |