Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7912738 |
1 |
|
|
T22 |
37660 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5793701 |
1 |
|
|
T22 |
28610 |
|
T27 |
144 |
|
T2 |
11448 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11260277 |
1 |
|
|
T22 |
49647 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
2446162 |
1 |
|
|
T22 |
16623 |
|
T27 |
179 |
|
T2 |
4351 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7905398 |
1 |
|
|
T22 |
38731 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5801041 |
1 |
|
|
T22 |
27539 |
|
T27 |
318 |
|
T1 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1686613 |
1 |
|
|
T22 |
5547 |
|
T27 |
88 |
|
T1 |
7 |
| auto[1] |
auto[0] |
auto[1] |
1221989 |
1 |
|
|
T22 |
7938 |
|
T27 |
107 |
|
T2 |
2307 |
| auto[1] |
auto[1] |
auto[0] |
1668266 |
1 |
|
|
T22 |
5369 |
|
T27 |
51 |
|
T2 |
2779 |
| auto[1] |
auto[1] |
auto[1] |
1224173 |
1 |
|
|
T22 |
8685 |
|
T27 |
72 |
|
T2 |
2044 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |