Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7876645 |
1 |
|
|
T22 |
37043 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5829794 |
1 |
|
|
T22 |
29227 |
|
T27 |
195 |
|
T1 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11243063 |
1 |
|
|
T22 |
49293 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
2463376 |
1 |
|
|
T22 |
16977 |
|
T27 |
141 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7863889 |
1 |
|
|
T22 |
38391 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5842550 |
1 |
|
|
T22 |
27879 |
|
T27 |
287 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1693114 |
1 |
|
|
T22 |
5140 |
|
T27 |
82 |
|
T1 |
1 |
| auto[1] |
auto[0] |
auto[1] |
1231125 |
1 |
|
|
T22 |
8228 |
|
T27 |
78 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1686060 |
1 |
|
|
T22 |
5762 |
|
T27 |
64 |
|
T2 |
3230 |
| auto[1] |
auto[1] |
auto[1] |
1232251 |
1 |
|
|
T22 |
8749 |
|
T27 |
63 |
|
T2 |
2690 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |