Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7846471 |
1 |
|
|
T22 |
36477 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5859968 |
1 |
|
|
T22 |
29793 |
|
T27 |
257 |
|
T1 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11247116 |
1 |
|
|
T22 |
48752 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
2459323 |
1 |
|
|
T22 |
17518 |
|
T27 |
85 |
|
T1 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7861348 |
1 |
|
|
T22 |
37151 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5845091 |
1 |
|
|
T22 |
29119 |
|
T27 |
176 |
|
T1 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1684605 |
1 |
|
|
T22 |
5740 |
|
T27 |
49 |
|
T2 |
2771 |
| auto[1] |
auto[0] |
auto[1] |
1225740 |
1 |
|
|
T22 |
8447 |
|
T27 |
48 |
|
T1 |
9 |
| auto[1] |
auto[1] |
auto[0] |
1701163 |
1 |
|
|
T22 |
5861 |
|
T27 |
42 |
|
T2 |
2987 |
| auto[1] |
auto[1] |
auto[1] |
1233583 |
1 |
|
|
T22 |
9071 |
|
T27 |
37 |
|
T1 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |