Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7903293 |
1 |
|
|
T22 |
37109 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5803146 |
1 |
|
|
T22 |
29161 |
|
T27 |
221 |
|
T1 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11264524 |
1 |
|
|
T22 |
49105 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
2441915 |
1 |
|
|
T22 |
17165 |
|
T27 |
121 |
|
T1 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7892623 |
1 |
|
|
T22 |
37757 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5813816 |
1 |
|
|
T22 |
28513 |
|
T27 |
242 |
|
T1 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1697298 |
1 |
|
|
T22 |
6116 |
|
T27 |
79 |
|
T1 |
3 |
| auto[1] |
auto[0] |
auto[1] |
1221340 |
1 |
|
|
T22 |
8840 |
|
T27 |
77 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1674603 |
1 |
|
|
T22 |
5232 |
|
T27 |
42 |
|
T2 |
3280 |
| auto[1] |
auto[1] |
auto[1] |
1220575 |
1 |
|
|
T22 |
8325 |
|
T27 |
44 |
|
T2 |
2528 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |