Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7873816 |
1 |
|
|
T22 |
36929 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5832623 |
1 |
|
|
T22 |
29341 |
|
T27 |
299 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11257367 |
1 |
|
|
T22 |
48224 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
2449072 |
1 |
|
|
T22 |
18046 |
|
T27 |
199 |
|
T2 |
4540 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7897768 |
1 |
|
|
T22 |
36546 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5808671 |
1 |
|
|
T22 |
29724 |
|
T27 |
425 |
|
T1 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1674472 |
1 |
|
|
T22 |
5605 |
|
T27 |
115 |
|
T1 |
9 |
| auto[1] |
auto[0] |
auto[1] |
1223202 |
1 |
|
|
T22 |
8625 |
|
T27 |
78 |
|
T2 |
2569 |
| auto[1] |
auto[1] |
auto[0] |
1685127 |
1 |
|
|
T22 |
6073 |
|
T27 |
111 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1225870 |
1 |
|
|
T22 |
9421 |
|
T27 |
121 |
|
T2 |
1971 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |