Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7853893 |
1 |
|
|
T22 |
37748 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5852546 |
1 |
|
|
T22 |
28522 |
|
T27 |
216 |
|
T2 |
12471 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11239240 |
1 |
|
|
T22 |
48844 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
2467199 |
1 |
|
|
T22 |
17426 |
|
T27 |
113 |
|
T1 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7835153 |
1 |
|
|
T22 |
37086 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5871286 |
1 |
|
|
T22 |
29184 |
|
T27 |
206 |
|
T1 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1700486 |
1 |
|
|
T22 |
6249 |
|
T27 |
40 |
|
T1 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1230077 |
1 |
|
|
T22 |
9022 |
|
T27 |
48 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1703601 |
1 |
|
|
T22 |
5509 |
|
T27 |
53 |
|
T2 |
3598 |
| auto[1] |
auto[1] |
auto[1] |
1237122 |
1 |
|
|
T22 |
8404 |
|
T27 |
65 |
|
T2 |
2616 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |