Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7867315 |
1 |
|
|
T22 |
38247 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5839124 |
1 |
|
|
T22 |
28023 |
|
T27 |
200 |
|
T1 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11251900 |
1 |
|
|
T22 |
48286 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
2454539 |
1 |
|
|
T22 |
17984 |
|
T27 |
105 |
|
T1 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7874013 |
1 |
|
|
T22 |
36517 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5832426 |
1 |
|
|
T22 |
29753 |
|
T27 |
247 |
|
T1 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1677723 |
1 |
|
|
T22 |
6487 |
|
T27 |
67 |
|
T1 |
8 |
| auto[1] |
auto[0] |
auto[1] |
1226110 |
1 |
|
|
T22 |
9971 |
|
T27 |
54 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1700164 |
1 |
|
|
T22 |
5282 |
|
T27 |
75 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1228429 |
1 |
|
|
T22 |
8013 |
|
T27 |
51 |
|
T2 |
2517 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |