Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7848827 |
1 |
|
|
T22 |
36744 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5857612 |
1 |
|
|
T22 |
29526 |
|
T27 |
45 |
|
T1 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11246505 |
1 |
|
|
T22 |
48632 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
2459934 |
1 |
|
|
T22 |
17638 |
|
T27 |
70 |
|
T1 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7869044 |
1 |
|
|
T22 |
36624 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5837395 |
1 |
|
|
T22 |
29646 |
|
T27 |
129 |
|
T1 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1682389 |
1 |
|
|
T22 |
5864 |
|
T27 |
59 |
|
T1 |
6 |
| auto[1] |
auto[0] |
auto[1] |
1229561 |
1 |
|
|
T22 |
8591 |
|
T27 |
68 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[0] |
1695072 |
1 |
|
|
T22 |
6144 |
|
T1 |
2 |
|
T2 |
2896 |
| auto[1] |
auto[1] |
auto[1] |
1230373 |
1 |
|
|
T22 |
9047 |
|
T27 |
2 |
|
T2 |
2377 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |