Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7889847 |
1 |
|
|
T22 |
38570 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5816592 |
1 |
|
|
T22 |
27700 |
|
T27 |
217 |
|
T2 |
10613 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11254615 |
1 |
|
|
T22 |
48326 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
2451824 |
1 |
|
|
T22 |
17944 |
|
T27 |
104 |
|
T1 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7870747 |
1 |
|
|
T22 |
36606 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5835692 |
1 |
|
|
T22 |
29664 |
|
T27 |
220 |
|
T1 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1695089 |
1 |
|
|
T22 |
6159 |
|
T27 |
68 |
|
T1 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1228460 |
1 |
|
|
T22 |
9433 |
|
T27 |
61 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1688779 |
1 |
|
|
T22 |
5561 |
|
T27 |
48 |
|
T2 |
3201 |
| auto[1] |
auto[1] |
auto[1] |
1223364 |
1 |
|
|
T22 |
8511 |
|
T27 |
43 |
|
T2 |
2481 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |