Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7878341 |
1 |
|
|
T22 |
37741 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5828098 |
1 |
|
|
T22 |
28529 |
|
T27 |
358 |
|
T1 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12958833 |
1 |
|
|
T22 |
62249 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
747606 |
1 |
|
|
T22 |
4021 |
|
T27 |
32 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7870374 |
1 |
|
|
T22 |
36693 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5836065 |
1 |
|
|
T22 |
29577 |
|
T27 |
193 |
|
T1 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2536219 |
1 |
|
|
T22 |
13513 |
|
T27 |
59 |
|
T1 |
7 |
| auto[1] |
auto[0] |
auto[1] |
371960 |
1 |
|
|
T22 |
2172 |
|
T27 |
12 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2552240 |
1 |
|
|
T22 |
12043 |
|
T27 |
102 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[1] |
375646 |
1 |
|
|
T22 |
1849 |
|
T27 |
20 |
|
T2 |
913 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |