Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7872995 |
1 |
|
|
T22 |
35984 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5833444 |
1 |
|
|
T22 |
30286 |
|
T27 |
344 |
|
T1 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11255970 |
1 |
|
|
T22 |
48744 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
2450469 |
1 |
|
|
T22 |
17526 |
|
T27 |
65 |
|
T1 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7892936 |
1 |
|
|
T22 |
37145 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5813503 |
1 |
|
|
T22 |
29125 |
|
T27 |
120 |
|
T1 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1676769 |
1 |
|
|
T22 |
5561 |
|
T27 |
22 |
|
T2 |
3057 |
| auto[1] |
auto[0] |
auto[1] |
1227002 |
1 |
|
|
T22 |
8885 |
|
T27 |
33 |
|
T1 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1686265 |
1 |
|
|
T22 |
6038 |
|
T27 |
33 |
|
T2 |
2733 |
| auto[1] |
auto[1] |
auto[1] |
1223467 |
1 |
|
|
T22 |
8641 |
|
T27 |
32 |
|
T2 |
2510 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |