Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7863614 |
1 |
|
|
T22 |
37282 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5842825 |
1 |
|
|
T22 |
28988 |
|
T27 |
262 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11258040 |
1 |
|
|
T22 |
48738 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
2448399 |
1 |
|
|
T22 |
17532 |
|
T27 |
149 |
|
T1 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7882724 |
1 |
|
|
T22 |
36688 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5823715 |
1 |
|
|
T22 |
29582 |
|
T27 |
323 |
|
T1 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1692754 |
1 |
|
|
T22 |
6322 |
|
T27 |
69 |
|
T2 |
2860 |
| auto[1] |
auto[0] |
auto[1] |
1230587 |
1 |
|
|
T22 |
8943 |
|
T27 |
54 |
|
T1 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1682562 |
1 |
|
|
T22 |
5728 |
|
T27 |
105 |
|
T2 |
3406 |
| auto[1] |
auto[1] |
auto[1] |
1217812 |
1 |
|
|
T22 |
8589 |
|
T27 |
95 |
|
T1 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |