Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7875724 |
1 |
|
|
T22 |
37179 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5830715 |
1 |
|
|
T22 |
29091 |
|
T27 |
231 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11262044 |
1 |
|
|
T22 |
48514 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
2444395 |
1 |
|
|
T22 |
17756 |
|
T27 |
148 |
|
T1 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7884921 |
1 |
|
|
T22 |
36685 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5821518 |
1 |
|
|
T22 |
29585 |
|
T27 |
297 |
|
T1 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1687105 |
1 |
|
|
T22 |
5919 |
|
T27 |
82 |
|
T1 |
3 |
| auto[1] |
auto[0] |
auto[1] |
1217858 |
1 |
|
|
T22 |
9539 |
|
T27 |
75 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1690018 |
1 |
|
|
T22 |
5910 |
|
T27 |
67 |
|
T2 |
2607 |
| auto[1] |
auto[1] |
auto[1] |
1226537 |
1 |
|
|
T22 |
8217 |
|
T27 |
73 |
|
T2 |
2252 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |