Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7884464 |
1 |
|
|
T22 |
36349 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5821975 |
1 |
|
|
T22 |
29921 |
|
T27 |
109 |
|
T1 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12966547 |
1 |
|
|
T22 |
62087 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
739892 |
1 |
|
|
T22 |
4183 |
|
T27 |
49 |
|
T2 |
1863 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7904350 |
1 |
|
|
T22 |
35985 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5802089 |
1 |
|
|
T22 |
30285 |
|
T27 |
252 |
|
T1 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2537839 |
1 |
|
|
T22 |
12918 |
|
T27 |
180 |
|
T2 |
4746 |
| auto[1] |
auto[0] |
auto[1] |
370942 |
1 |
|
|
T22 |
2090 |
|
T27 |
45 |
|
T2 |
866 |
| auto[1] |
auto[1] |
auto[0] |
2524358 |
1 |
|
|
T22 |
13184 |
|
T27 |
23 |
|
T1 |
5 |
| auto[1] |
auto[1] |
auto[1] |
368950 |
1 |
|
|
T22 |
2093 |
|
T27 |
4 |
|
T2 |
997 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |