Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7874558 |
1 |
|
|
T22 |
35279 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5831881 |
1 |
|
|
T22 |
30991 |
|
T27 |
215 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12964407 |
1 |
|
|
T22 |
62453 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
742032 |
1 |
|
|
T22 |
3817 |
|
T27 |
67 |
|
T2 |
1658 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7899048 |
1 |
|
|
T22 |
37331 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5807391 |
1 |
|
|
T22 |
28939 |
|
T27 |
318 |
|
T1 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2533787 |
1 |
|
|
T22 |
11724 |
|
T27 |
146 |
|
T1 |
5 |
| auto[1] |
auto[0] |
auto[1] |
371164 |
1 |
|
|
T22 |
1758 |
|
T27 |
39 |
|
T2 |
842 |
| auto[1] |
auto[1] |
auto[0] |
2531572 |
1 |
|
|
T22 |
13398 |
|
T27 |
105 |
|
T2 |
4487 |
| auto[1] |
auto[1] |
auto[1] |
370868 |
1 |
|
|
T22 |
2059 |
|
T27 |
28 |
|
T2 |
816 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |