Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7871472 |
1 |
|
|
T22 |
35284 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5834967 |
1 |
|
|
T22 |
30986 |
|
T27 |
143 |
|
T2 |
11646 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12968464 |
1 |
|
|
T22 |
62356 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
737975 |
1 |
|
|
T22 |
3914 |
|
T27 |
71 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7919699 |
1 |
|
|
T22 |
36814 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5786740 |
1 |
|
|
T22 |
29456 |
|
T27 |
357 |
|
T1 |
14 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2529325 |
1 |
|
|
T22 |
12787 |
|
T27 |
193 |
|
T1 |
13 |
| auto[1] |
auto[0] |
auto[1] |
369578 |
1 |
|
|
T22 |
2014 |
|
T27 |
45 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2519440 |
1 |
|
|
T22 |
12755 |
|
T27 |
93 |
|
T2 |
4951 |
| auto[1] |
auto[1] |
auto[1] |
368397 |
1 |
|
|
T22 |
1900 |
|
T27 |
26 |
|
T2 |
974 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |