Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7896231 |
1 |
|
|
T22 |
35816 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5810208 |
1 |
|
|
T22 |
30454 |
|
T27 |
184 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12961018 |
1 |
|
|
T22 |
61998 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
745421 |
1 |
|
|
T22 |
4272 |
|
T27 |
52 |
|
T2 |
1899 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7870759 |
1 |
|
|
T22 |
34895 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5835680 |
1 |
|
|
T22 |
31375 |
|
T27 |
239 |
|
T1 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2553772 |
1 |
|
|
T22 |
13260 |
|
T27 |
137 |
|
T1 |
9 |
| auto[1] |
auto[0] |
auto[1] |
374071 |
1 |
|
|
T22 |
2114 |
|
T27 |
35 |
|
T2 |
1057 |
| auto[1] |
auto[1] |
auto[0] |
2536487 |
1 |
|
|
T22 |
13843 |
|
T27 |
50 |
|
T2 |
4572 |
| auto[1] |
auto[1] |
auto[1] |
371350 |
1 |
|
|
T22 |
2158 |
|
T27 |
17 |
|
T2 |
842 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |