Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7879451 |
1 |
|
|
T22 |
36456 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5826988 |
1 |
|
|
T22 |
29814 |
|
T27 |
256 |
|
T1 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12961300 |
1 |
|
|
T22 |
62365 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
745139 |
1 |
|
|
T22 |
3905 |
|
T27 |
27 |
|
T2 |
1785 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7877148 |
1 |
|
|
T22 |
36822 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5829291 |
1 |
|
|
T22 |
29448 |
|
T27 |
145 |
|
T1 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2546193 |
1 |
|
|
T22 |
12395 |
|
T27 |
64 |
|
T1 |
10 |
| auto[1] |
auto[0] |
auto[1] |
373337 |
1 |
|
|
T22 |
1879 |
|
T27 |
18 |
|
T2 |
888 |
| auto[1] |
auto[1] |
auto[0] |
2537959 |
1 |
|
|
T22 |
13148 |
|
T27 |
54 |
|
T1 |
5 |
| auto[1] |
auto[1] |
auto[1] |
371802 |
1 |
|
|
T22 |
2026 |
|
T27 |
9 |
|
T2 |
897 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |