Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7860752 |
1 |
|
|
T22 |
36302 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5845687 |
1 |
|
|
T22 |
29968 |
|
T27 |
365 |
|
T2 |
11604 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12961864 |
1 |
|
|
T22 |
62158 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
744575 |
1 |
|
|
T22 |
4112 |
|
T27 |
58 |
|
T2 |
1750 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7880995 |
1 |
|
|
T22 |
35985 |
|
T23 |
930 |
|
T24 |
1336 |
| auto[1] |
5825444 |
1 |
|
|
T22 |
30285 |
|
T27 |
295 |
|
T1 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2541392 |
1 |
|
|
T22 |
13294 |
|
T27 |
90 |
|
T1 |
1 |
| auto[1] |
auto[0] |
auto[1] |
372909 |
1 |
|
|
T22 |
2095 |
|
T27 |
21 |
|
T2 |
784 |
| auto[1] |
auto[1] |
auto[0] |
2539477 |
1 |
|
|
T22 |
12879 |
|
T27 |
147 |
|
T2 |
5067 |
| auto[1] |
auto[1] |
auto[1] |
371666 |
1 |
|
|
T22 |
2017 |
|
T27 |
37 |
|
T2 |
966 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |